Freescale Semiconductor MCF5480 - Manual (Page 534)

MCF548x Reference Manual, Rev. 3
19-50 Freescale Semiconductor
command driven on the PCICXBE bus. In cycle 2, the AD bus is in a turnaround cycle because of the read
on a muxed bus. The byte enables, which are active low, are driven onto the PCICXBE bus in this clock.
Any combination of byte enables can be asserted (none may be asserted). A target will respond to an
address phase by driving the DEVSEL signal. The specification allows for four types of decode operations.
The target can drive DEVSEL in 1, 2, or 3 clocks depending on whether the target is a fast, medium or
slow decode device, respectively. A single device is allowed to drive DEVSEL if no other agent responds
by the fourth clock. This is called “subtractive decoding” in PCI terminology. Note that the MCF548x is
a medium target decode device.
A valid transfer occurs when both PCIIRDY and PCITRDY are asserted. If either are negated during a
data phase, it is considered a wait state. The target asserts a wait state in cycles 3 and 5 of Figure 19-47 . A
master indicates that the final data phase is to occur by negating PCIFRAME. In this diagram the target
responds as a medium device, driving DEVSEL in cycle 3.
The final data phase occurs in cycle 6. Another agent cannot start an access until cycle 8. A provision in
the specification allows the current master to start another transfer in cycle 7 when certain conditions
apply. Refer to “fast back-to-back transfers” in the PCI specification for more details.
Figure 19-47. PCI Read Terminated by Master
Figure 19-48 shows a write cycle which is terminated by the target. In this diagram the target responds as
a slow device, driving DEVSEL in cycle 4. The first data is transferred in cycle 4. The master inserts a
wait state at cycle 5. The target indicates that it can accept only one more transfer by asserting both
PCITRDY and PCISTOP at the same time in cycle 5. The signal PCISTOP must remain asserted until
PCIFRAME negates. The final data phase does not have to transfer data. If PCISTOP and PCIIRDY are
both asserted while PCITRDY is negated, it is considered a target disconnect without a transfer. See the
PCI specification for more details.
Address
Phase
PCI_CLK
FRAME
PCIAD
PCICXBE
PCIIRDY
PCITRDY
0 1 2 3 4 5 6 7 8
DEVSEL
Data
A1 D1 D2
CMD BYTE ENABLES
9
Phase 2
Data
Phase 1
(Wait) (Wait)
BYTE ENABLES