Freescale Semiconductor MCF5480 - Manual (Page 14)

MCF548x Reference Manual, Rev. 3
xiv Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
8.4.5 Address Attribute Trigger Registers (AATR, AATR1) ............................................ 8-16
8.4.6 Trigger Definition Register (TDR) ........................................................................... 8-17
8.4.7 Program Counter Breakpoint and Mask Registers (PBR n , PBMR) ......................... 8-20
8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ........................... 8-21
8.4.9 Data Breakpoint and Mask Registers (DBR/DBR1, DBMR/DBMR1) .................... 8-22
8.4.10 PC Breakpoint ASID Register (PBASID) ................................................................ 8-24
8.4.11 Extended Trigger Definition Register (XTDR) ........................................................ 8-25
8.4.11.1 Resulting Set of Possible Trigger Combinations .................................................. 8-27
8.5 Background Debug Mode (BDM) ................................................................................ 8-28
8.5.1 CPU Halt ................................................................................................................... 8-28
8.5.2 BDM Serial Interface ................................................................................................ 8-30
8.5.2.1 Receive Packet Format ......................................................................................... 8-30
8.5.2.2 Transmit Packet Format ........................................................................................ 8-31
8.5.3 BDM Command Set .................................................................................................. 8-31
8.5.3.1 ColdFire BDM Command Format ........................................................................ 8-33
8.5.3.2 Command Sequence Diagrams ............................................................................. 8-33
8.5.3.3 Command Set Descriptions .................................................................................. 8-35
8.6 Real-Time Debug Support ............................................................................................ 8-51
8.6.1 Theory of Operation .................................................................................................. 8-51
8.6.1.1 Emulator Mode ..................................................................................................... 8-53
8.6.2 Concurrent BDM and Processor Operation .............................................................. 8-53
8.7 Debug C Definition of PSTDDATA Outputs .............................................................. 8-54
8.7.1 User Instruction Set .................................................................................................. 8-54
8.7.2 Supervisor Instruction Set ......................................................................................... 8-60
8.8 ColdFire Debug History ................................................................................................ 8-61
8.8.1 ColdFire Debug Classic: The Original Definition .................................................... 8-61
8.8.2 ColdFire Debug Revision B ...................................................................................... 8-62
8.8.3 ColdFire Debug Revision C ...................................................................................... 8-62
8.8.3.1 Debug Interrupts and Interrupt Requests (Emulator Mode) ................................. 8-62
8.9 Freescale-Recommended BDM Pinout ........................................................................ 8-63
Chapter 9
System Integration Unit (SIU)
9.1 Introduction ..................................................................................................................... 9-1
9.2 Features ........................................................................................................................... 9-1
9.3 Memory Map/Register Definition .................................................................................. 9-1
9.3.1 Module Base Address Register (MBAR) ................................................................... 9-2
9.3.1.1 System Breakpoint Control Register (SBCR) ........................................................ 9-3
9.3.1.2 SEC Sequential Access Control Register (SECSACR) ......................................... 9-4
9.3.1.3 Reset Status Register (RSR) ................................................................................... 9-5