Freescale Semiconductor MCF5480 User Manual
Page 957
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
30-27
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IP
0
0
0
FRM
FAE
RXW
UF
OF
FRM
RDY
FU
ALARM EMT
W
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x9188 (FEC0), 0x9988 (FEC1)
Figure 30-22. FEC Receive FIFO Status Register (FECRFSR)
Table 30-26. FECRFSR Field Descriptions
Bits
Name
Descriptions
31
IP
Illegal pointer. This bit signifies an illegal pointer condition in the FIFO controller. For example, if a
value larger than the FIFO controller’s range is written to a Read, Write, Last Read, or Last Write
Pointer, the IP bit will assert. If not masked, a one in this bit will cause a RFERR in the EIR. This bit
will remain set until a 1 is written to this bit location.
0 No illegal pointer condition.
1 An address outside the FIFO controller’s memory range has been written to one of the user-visible
pointers.
This bit should always be 0 on the FEC since the receive FIFO size is fixed.
30-28
—
Reserved, should be cleared.
27–24
FRM
Frame indicator. This read-only field provides a frame status indicator for non-DMA applications.
1000 A frame boundary has occurred on the [31:24] byte of the data bus
0100 A frame boundary has occurred on the [23:16] byte of the data bus
0010 A frame boundary has occurred on the [15:8] byte of the data bus
0001 A frame boundary has occurred on the [7:0] byte of the data bus
23
FAE
Frame accept error. This bit indicates a frame accept error in the FIFO controller and will set if data
is read from a receive FIFO for a frame that has subsequently been rejected. If not masked, a one
in this bit will cause a RFERR in the EIR. This bit will remain set until a one is written to this bit
location. This bit is inactive when the FIFO is not programmed for frame mode.
0 No frame accept error.
1 Frame accept error. Writing a one clears this bit.
22
RXW
Receive wait condition. This bit indicates that the FEC internal bus connected to the FIFO is incurring
wait states because there is not enough room in the FIFO to accept the data without causing
overflow. If not masked, a one in this bit will cause a RFERR in the EIR. This bit will remain set until
a 1 is written to this bit location.
0 No wait condition.
1 When the FIFO is full and the FEC received more data. Writing a one to this bit clears this bit.