Freescale Semiconductor MCF5480 User Manual
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Exception Processing Overview
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
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Unimplemented
line-a opcode
A line-a opcode results when bits 15–12 of the opword are 1010. This exception is generated by the
attempted execution of an undefined line-a opcode.
Unimplemented
line-f opcode
A line-f opcode results when bits 15–12 of the opword are 1111. This exception is generated under the
following conditions:
• When attempting to execute an undefined line-f opcode.
• When attempting to execute an FPU instruction when the FPU has been disabled in the CACR.
Debug interrupt The debug interrupt exception is caused by a hardware breakpoint register trigger. Rather than generating
an IACK cycle, the processor internally calculates the vector number (12 or 13, depending on the type of
breakpoint trigger). Additionally, SR[M,I] are unaffected by the interrupt.
Separate exception vectors are provided for PC breakpoints and for address/data breakpoints. In the case of
a two-level trigger, the last breakpoint determines the vector. The two unique entries occur when a PC
breakpoint generates the 0x034 vector. In case of a two-level trigger, the last breakpoint event determines
the vector. See
for more information.
Format error
When an RTE instruction executes, the processor first examines the 4-bit format field to validate the frame
type. For a ColdFire processor, attempted execution of an RTE where the format is not equal to {4, 5, 6, 7}
generates a format error. The exception stack frame for the format error is created without disturbing the
original exception frame and the stacked PC points to RTE. The selection of the format value provides limited
debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the
top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero. Attempting an
RTE using this old format generates a format error on a ColdFire processor. If the format field defines a valid
type, the processor does the following:
1 Reloads the SR operand.
2 Fetches the second longword operand.
3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first
longword fetch.
4 Transfers control to the instruction address defined by the second longword operand in the stack frame.
When the processor executes a FRESTORE instruction, if the restored FPU state frame contains a
non-supported value, execution is aborted and a format error exception is generated.
Trap
Executing a TRAP instruction always forces an exception and is useful for implementing system calls. The
trap instruction may be used to change from user to supervisor mode.
Interrupt
exception
Please refer to
Section Chapter 13, “Interrupt Controller.”
Reset exception Asserting the reset input signal (RSTI) causes a reset exception, which has the highest exception priority and
provides for system initialization and recovery from catastrophic failure. When assertion of RSTI is
recognized, current processing is aborted and cannot be recovered. The reset exception places the
processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T]. It clears SR[M] and
sets SR[I] to the highest level (0b111, priority level 7). Next, VBR is cleared. Configuration registers
controlling operation of all processor-local memories are invalidated, disabling the memories.
Note: Implementation-specific supervisor registers are also affected at reset.
After RSTI is negated, the processor waits 16 cycles before beginning the reset exception process. During
this time, certain events are sampled, including the assertion of the debug breakpoint signal. If the processor
is not halted, it initiates the reset exception by performing two longword read bus cycles. The longword at
address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC. After the initial
instruction is fetched from memory, program execution begins at the address in the PC. If an access error or
address error occurs before the first instruction executes, the processor enters a fault-on-fault halted state.
Unsupported
instruction
exception
If the CF4e attempts to execute a valid instruction but the required optional hardware module is not present
in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is then passed to an
exception handler that can then process the opcode as required by the system.
Table 3-23. Processor Exceptions (Continued)
Type
Description