Freescale Semiconductor MCF5480 - Manual (Page 56)

MCF548x Reference Manual, Rev. 3
lvi Freescale Semiconductor
27.6.1/27-5 Remove instances of MDIS bit as it is not present on this version of the DSPI.
Table 29-3/29-11 USBCR[APPLOCK] bit description, the bit setting numbers are incorrrect. When cleared (0), APPLOCK is
deasserted. When set (1), APPLOCK is asserted.
Table 29-29/29-30 Endpoint status register’s PSTALL entry: the last sentence should be “Setting this bit also sets
USBAISR[EPSTALL].” instead of “Setting this bit also sets USBAISR[EPHALT].”
Table 29-37/29-36 EPnISR[EOT] bit description, add a note to the last sentence of the first paragraph stating “The EOT
interrupt will not assert for an isochronous OUT packet that experiences a PID sequencing error.”
29.4.3.1/29-51 Add a section below USB Packets entitled “Handshakes” with the following paragraphs:
“The USB device will return a NYET handshake packet to an OUT transaction if there is already data
present in the FIFO and there are less than 2*MAXPACKETSIZE bytes free in the FIFO.
In cases where the FIFO depth is larger than 2*MAXPACKETSIZE (i.e. 3x or 4x), the following behavior
will occur. If after a transfer that returned a NYET handshake there is at least 1*MAXPACKETSIZE of free
space in the FIFO, the device will ACK the first PING request from the host and accept another
MAXPACKETSIZE transfer from the host. The device will again send a NYET handshake.
The only time the device will NAK a PING is when there is less than 1*MAXPACKETSIZE of free space in
the FIFO.”
Table 30-41/30-42 Change bit description of the FECFRST[SW_RST] bit to “Software Reset - This bit controls the soft reset
of the FEC FIFOs. A soft reset will reset the FIFO pointers and byte counters but not the status and control
registers. To cause a soft reset this bit should be set and then cleared by application software.”
Change bit description of the FECFRST[RST_CTL] bit to “Reset control - Setting this bit allows the FEC
controller to perform a soft reset of the FIFOs when the FEC is disabled (ECR[ETHER_EN] cleared).”
Table 31-1/31-1 Add column to indicate whether the signal has a pull-up resistor.
These signals have a pull-up resistor at all times:
DSCLK/TRST, BKPT/TMS, DSI/TDI
These signals have a pull-up resistor whenever configured for general-purpose input (default state after
reset):
PCIBR[4:3], PCIGNT[4:3], E1MDIO, E1MDC, E1TXCLK, E1TXEN, E1TXD[3:0], E1COL, E1RXCLK,
E1RXDV, E1RXD[3:0], E1CRS, E1TXER, E1RXER
Table 31-1/31-1 Ball P3 should be SD_VDD instead of EVDD.
Table 31-1/31-1 The GPIO bit number for each of the UART control signals are incorrect for Table 31-1. However, they are
correct for Table 2-1:
• Y23/PSC1RTS pin: Change GPIO entry from PPSCL7 to PPSC1PSC06.
• AB23/PSC3RTS pin: Change GPIO entry from PPSCH7 to PPSC3PSC26.
• AB26/PSC0RTS pin: Change GPIO entry from PPSCL3 to PPSC1PSC02.
• AC19/PSC2CTS pin: Change GPIO entry from PPSCH2 to PPSC3PSC23.
• AD26/PSC2RTS pin: Change GPIO entry from PPSCH3 to PPSC3PSC22.
• AE23/PSC0CTS pin: Change GPIO entry from PPSCL2 to PPSC1PSC03.
• AF23/PSC3CTS pin: Change GPIO entry from PPSCH6 to PPSC3PSC27.
• AF25/PSC1CTS pin: Change GPIO entry from PPSCL6 to PPSC1PSC07.
Table 31-1/31-1 Remove overbar from ALE at location AD6.
Table 31-1/31-1 • Replace PPSCLn entries under the GPIO column with PPSC1PSC0n. There is no PPSCL port.
• Replace PPSCHn entries under the GPIO column with PPSC3PSC2n. There is no PPSCH port.
Table iv. MCF548x Revision History (continued)
Section/Page Substantive Changes