Freescale Semiconductor MCF5480 - Manual (Page 344)

MCF548x Reference Manual, Rev. 3
11-4 Freescale Semiconductor
15 WDEN Watchdog enable. Enables watchdog operation. A timer expiration causes an internal MCF548x
reset. Watchdog operation requires the TMS field be set for internal timer mode and the CE bit to be
set.
In this mode the OCPW byte field operates as a watchdog reset field. Writing A5 to the OCPW field
resets the watchdog timer, preventing it from expiring. As long as the timer is properly configured, the
watchdog operation continues.
This bit (and functionality) is implemented only for GPT0.
0 Watchdog not enabled
1 Watchdog enabled
14–13 — Reserved, should be cleared.
12 CE Counter enable. Enables or resets the internal counter during internal timer modes only. CE must be
set to enable these modes. If cleared, counter is held in reset.
0 Timer counter held in reset
1 Timer counter enabled
This bit is secondary to the timer mode select bits (TMS). If TMS is1XX, internal timer modes are
enabled. CE can then enable or reset the internal counter without changing the TMS field.
GPIO operation is also available in this mode.
11 — Reserved, should be cleared.
10 SC Stop/continuous mode.
0 Stops the operation
1 Continues the operation
The SC bit applies to multiple modes, as follows:
IC mode (input capture mode)
Stop operation—At each IC event, counter is reset.
Continuous operation—counter is not reset at each IC event.
Effect is to create status count values that are cumulative between capture events. If the special pulse
mode capture type is specified, the SC bit is not used, operation fixed as if it were stop.
OC mode (output capture mode)
Stop operation—Counter resets and stops at the first output capture event. Software needs to pass
through TMS=000 state to restart timer.
Continuous operation—counter resets and continues at each OC event. The effect to is create
back-to-back periodic OC events.
PWM mode (pulse width modulation mode)
The SC bit is not used; operation is always continuous.
CPU Timer mode
Stop operation—On counter expiration, timer waits until status bit is cleared by passing through
TMS=000 state before beginning a new cycle.
Continuous operation—On counter expiration, timer resets and immediately begin a new cycle. The
effect is to generate fixed periodic timeouts.
WatchDog Timer and GPIO modes
The SC bit is not used.
9 OD Open drain.
0 Normal I/O
1 Open Drain emulation—affects all modes that drive the I/O pin (GPIO, OC, and PWM). Any output
“1” is converted to a tri-state at the I/O pin.
Table 11-2. GMSn Field Descriptions (Continued)
Bits Name Description