Freescale Semiconductor MCF5480 - Manual (Page 245)

Cache Management
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-25
dataCacheLoadAndLock:
move.l #0xa3080800,d0; enable and invalidate data cache ...
movec d0,cacr ; ... in the CACR
The following code preloads half of the data cache (16 Kbytes). It assumes a contiguous block of data is
to be mapped into the data cache, starting at a 0-modulo-16K address.
move.l #1024,d0 ;256 16-byte lines in 16K space
lea data_,a0 ; load pointer defining data area
dataCacheLoop:
tst.b (a0) ;touch location + load into data cache
lea 16(a0),a0;increment address to next line
subq.l #1,d0 ;decrement loop counter
bne.b dataCacheLoop;if done, then exit, else continue
; A 16K region has been loaded into ways 0 and 1 of the 32K data cache. lock it!
move.l #0xaa088000,d0;set the data cache lock bit ...
movec d0,cacr ; ... in the CACR
rts
align 16
The following CACR loads assume the data cache has been invalidated, the default instruction cache mode
is cacheable and the default operand cache mode is copyback.
Note that this function must be mapped into a cache inhibited or SRAM space, or these text lines will be
prefetched into the instruction cache, possibly displacing some of the 8-Kbyte space being explicitly
fetched.
instructionCacheLoadAndLock:
move.l #0xa2088100,d0;enable and invalidate the instruction
movec d0,cacr ;cache in the CACR
The following code segments preload half of the instruction cache (8 Kbytes). It assumes a contiguous
block of data is to be mapped, starting at a 0-modulo-8K address
move.l #512,d0 ;512 16-byte lines in 8K space
lea code_,a0 ;load pointer defining code area
instCacheLoop:
intouch (a0) ;touch location + load into instruction cache
; Note in the assembler we use, there is no INTOUCH opcode. The following
; is used to produce the required binary representation
cpushl #nc,(a0) ;touch location + load into
;instruction cache
lea 16(a0),a0;increment address to next line
subq.l #1,d0 ;decrement loop counter
bne.b instCacheLoop;if done, then exit, else continue
; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. ; lock it!
move.l #0xa2088800,d0;set the instruction cache lock bit
movec d0,cacr ;in the CACR
rts