Freescale Semiconductor MCF5480 - Manual (Page 241)

Cache Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-21
13 DNFB Default cache-inhibited fill buffer
0 Fill buffer does not store cache-inhibited instruction accesses (16 or 32 bits).
1 Fill buffer can store cache-inhibited accesses. The buffer is used only for normal (TT = 0)
instruction reads of a cache-inhibited region. Instructions are loaded into the buffer by a burst
access (line fill). They stay in the buffer until they are displaced; subsequent accesses may not
appear on the external bus.
Setting DNFB can cause a coherency problem for self-modifying code. If a cache-inhibited access
uses the buffer while DNFB = 1, instructions remain valid in the buffer until a cache-invalidate-all
instruction, another cache-inhibited burst, or a miss that initiates a fill. A write to the line in the fill
goes to the external bus without updating or invalidating the buffer. Subsequent reads of that written
data are serviced by the fill buffer and receive stale information.
Note: Freescale discourages the use of self-modifying code.
12 IDPI Instruction CPUSHL invalidate disable.
0 Normal operation. A CPUSHL instruction causes the selected line to be invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be left valid.
11 IHLCK Instruction cache half-lock.
0 Normal operation. The cache allocates to the lowest invalid way; if all ways are valid, the cache
allocates to the way pointed at by the round-robin counter and then increments this counter.
1 Half cache operation. The cache allocates to the lowest invalid way of ways 2 and 3; if both of
these ways are valid, the cache allocates to way 2 if the high-order bit of the round-robin counter
is zero; otherwise, it allocates way 3 and then increments the round-robin counter. This locks the
contents of ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or
cleared by specific cache push/invalidate instructions.
10 IDCM Instruction default cache mode. For normal operations that do not hit in the RAMBARs or ACRs, this
field defines the effective cache mode.
0 Cacheable
1 Cache-inhibited
9 — Reserved, should be cleared.
8 ICINVA Instruction cache invalidate. Invalidation occurs when this bit is written as a 1. Note the caches are
not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate invalidation of instruction cache. The cache controller sequentially clears all V bits.
Subsequent local memory bus accesses stall until invalidation completes, at which point ICINVA
is cleared automatically without software intervention. For copyback mode, use CPUSHL before
setting ICINVA.
7 IDSP Default instruction supervisor protection bit. For normal operations that do not hit in the RAMBAR,
ROMBAR, or ACRs, this field defines supervisor-protection.
0 Not supervisor protected
1 Supervisor protected. User operations cause a fault
6 — Reserved, should be cleared.
5 EUSP Enable USP. Enables the use of the user stack pointer.
0 USP disabled. Core uses a single stack pointer.
1 USP enabled. Core uses separate supervisor and user stack pointers.
4 DF Disable FPU. Determines whether the FPU is enabled. See Section 6.1.1, “Overview.”
0 FPU enabled.
1 FPU disabled
3–0 — Reserved, should be cleared.
Table 7-4. CACR Field Descriptions (Continued)
Bits Name Description