Freescale Semiconductor MCF5480 - Manual (Page 967)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-37
30.3.3.29 FEC Transmit FIFO Last Read Frame Pointer Register (FECTLRFP)
The last read frame pointer (LRFP) is a FIFO-maintained pointer that indicates the location of the next
byte after the last frame that has been completely read. If no frames have been read out of the FIFO, the
register indicates the first byte location in the FIFO(the reset state). The LRFP updates on FIFO read data
accesses to a frame boundary. The LRFP updates on FIFO read data accesses to a frame boundary. The
LRFP can be read and written for debug purposes. For the frame retransmit function, the LRFP indicates
which point to begin retransmission of the data frame. The LRFP carries validity information, however,
there are no safeguards to prevent retransmitting data which has been overwritten. When
FECTFCR[FRMEN] is not set, then this pointer has no meaning. The last read frame pointer is reset to
zero, and non-functional bits of this pointer will always remain zero.
26–24 GR Last transfer granularity. A transmit alarm request is cleared when there are less than (4 * GR[2:0])
free bytes remaining in the FIFO.
23 IP_MSK llegal pointer mask. When this bit is set, the FIFO controller masks the status register’s IP bit from
generating a XFERR in the EIR.
22 FAE_MSK Frame accept error mask. When this bit is set, the FIFO controller masks the status register’s FAE
bit from generating an error.
21 — Reserverd, should be set.
20 UF_MSK FIFO underflow mask. When this bit is set, the FIFO controller masks the status register’s UF bit
from generating a XFERR in the EIR.
19 OF_MSK FIFO overflow mask. When this bit is set, the FIFO controller masks the status register’s OF bit
from generating a XFERR in the EIR.
18 TXW_MASK When this bit is set, the FIFO controller masks the Status Register’s TXW bit from generating an
error. (To help with backward compatibility, this bit is asserted at reset.)
17-16 — Reserved, should be cleared.
15–0 COUNTER Timer mode counter. When the TIMER bit is set, the value of the COUNTER[15:0] bits are used
to determine the period of time that the frame ready request is suppressed. A request for service
will be made every (COUNTER[15:0] * 64) cycles as long as a valid frame exists in the FIFO.
Table 30-35. FECTFCR Field Descriptions (Continued)
Bits Name Descriptions