Freescale Semiconductor MCF5480 - Manual (Page 29)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xxix
Contents
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Title
Page
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24.2.1 DREQ[1:0] ............................................................................................................... 24-3
24.2.2 DACK[1:0] .............................................................................................................. 24-3
24.3 Memory Map/Register Definitions ............................................................................... 24-3
24.3.1 DMA Task Memory .................................................................................................. 24-3
24.3.1.1 Task Table ............................................................................................................ 24-3
24.3.1.2 Task Descriptor Table ........................................................................................... 24-3
24.3.1.3 Variable Table ...................................................................................................... 24-4
24.3.1.4 Function Descriptor Table .................................................................................... 24-4
24.3.1.5 Context Save Space .............................................................................................. 24-4
24.3.2 Memory Structure ..................................................................................................... 24-4
24.3.3 DMA Registers ......................................................................................................... 24-5
24.3.3.1 DMA Register Map .............................................................................................. 24-5
24.3.3.2 Task Base Address Register (TaskBAR) .............................................................. 24-6
24.3.3.3 Current Pointer (CP) ............................................................................................. 24-7
24.3.3.4 End Pointer (EP) ................................................................................................... 24-8
24.3.3.5 Variable Pointer (VP) ........................................................................................... 24-8
24.3.3.6 PTD Control (PTD) .............................................................................................. 24-9
24.3.3.7 DMA Interrupt Pending (DIPR) ......................................................................... 24-10
24.3.3.8 DMA Interrupt Mask Register (DIMR) .............................................................. 24-10
24.3.3.9 Task Control Registers (TCRn) .......................................................................... 24-11
24.3.3.10 Priority Registers (PRIORn) ............................................................................... 24-12
24.3.3.11 Initiator Mux Control Register (IMCR) ............................................................. 24-13
24.3.3.12 Task Size Registers (TSKSZ[0:1]) ..................................................................... 24-14
24.3.3.13 Debug Comparator Registers (DBGCOMPn) .................................................... 24-16
24.3.3.14 Debug Control (DBGCTL) ................................................................................. 24-16
24.3.3.15 Debug Status (DBGSTAT) ................................................................................. 24-18
24.3.3.16 PTD Debug Registers ......................................................................................... 24-19
24.3.4 External Request Module Registers ........................................................................ 24-20
24.3.4.1 External Request Module Register Map ............................................................. 24-20
24.3.4.2 External Request Base Address Register (EREQBAR) ..................................... 24-20
24.3.4.3 External Request Address Mask Register (EREQMASK) ................................. 24-21
24.3.4.4 External Request Control Register (EREQCTRL) ............................................. 24-21
24.4 Functional Description ................................................................................................ 24-22
24.4.1 Tasks ....................................................................................................................... 24-22
24.4.2 Descriptors .............................................................................................................. 24-23
24.4.3 Task Initialization ................................................................................................... 24-23
24.4.4 Initiators .................................................................................................................. 24-23
24.4.5 Prioritization ........................................................................................................... 24-24
24.4.6 Context Switch ........................................................................................................ 24-24
24.4.7 Data Movement ....................................................................................................... 24-24
24.4.8 Data Manipulation .................................................................................................. 24-24