Freescale Semiconductor MCF5480 - Manual (Page 1024)

MCF548x Reference Manual, Rev. 3
Index-10 Freescale Semiconductor
infrared FIR divide (PSCIRFDRn) 26-26
infrared MIR divide (PSCIRMDRn) 26-25
infrared SIR divide (PSCIRSDRn) 26-25
input port (PSCIP) 26-21
input port (PSCIPn) 26-21
input port change (PSCIPCRn) 26-17
interrupt mask (PSCIMRn) 26-19
interrupt status (PSCISRn) 26-18
mode 1 (PSCMR1) 26-5
mode 1 (PSCMR1n) 26-5
mode 2 (PSCMR2n) 26-6
output port bit reset (PSCOPRESETn) 26-22
output port bit set (PSCOPSETn) 26-22
PSC/IrDA control (PSCSICRn) 26-23
receiver and transmitter buffer (PSCRBn,
PSCTBn) 26-14
RxFIFO and TxFIFO alarm (PSCRFARn,
PSCTFARn) 26-32
RxFIFO and TxFIFO control (PSCRFCRn,
PSCTFCRn) 26-30
RxFIFO and TxFIFO counter (PSCRFCRn,
PSCTFCRn) 26-27
RxFIFO and TxFIFO data (PSCRFDRn,
PSCTFDRn) 26-27
RxFIFO and TxFIFO last read frame pointer
(PSCRLRFPn, PSCTLRFPn) 26-33
RxFIFO and TxFIFO last write frame pointer
(PSCRLWFPn, PSCTLWFPn) 26-34
RxFIFO and TxFIFO read pointer (PSCRFRPn,
PSCTFRPn) 26-32
RxFIFO and TxFIFO status (PSCRFSRn,
PSCTFSRn) 26-28
RxFIFO and TxFIFO write pointer (PSCRFWPn,
PSCTFWPn) 26-33
status (PSCSRn) 26-8
SDRAM controller
chip select configuration (CSnCFG) 18-18
configuration 1 (SDCFG1) 18-21
configuration 2 (SDCFG2) 18-23
control (SDCR) 18-20
drive strength (SDRAMDS) 18-17
mode/extended mode (SDMR) 18-19
SEC
AESU interrupt mask (AESIMR) 22-54
AESU interrupt status (AESISR) 22-53
AESU reset control (AESRCR) 22-50
AESU status (AESSR) 22-51
AFEU interrupt mask (AFIMR) 22-32
AFEU interrupt status (AFISR) 22-31
AFEU reset control (AFRCR) 22-28
AFEU status (AFSR) 22-29
crypto-channel configuration (CCCRn) 22-19
crypto-channel current descriptor pointer
(CDPRn) 22-27
crypto-channel pointer status (CCPSRn) 22-21
data packet descriptor buffer (CDBUFn) 22-28
DEU interrupt mask (DIMR) 22-39
DEU interrupt status (DISR) 22-37
DEU reset control (DRCR) 22-34
DEU status (DSR) 22-35
EU assignment control (EUACR) 22-11
EU assignment status (EUASR) 22-13
fetch (FRn) 22-27
ID (SIDR) 22-16
interrupt control (SICR) 22-14
interrupt mask (SIMR) 22-14
interrupt status (SISR) 22-14
master control (SMCR) 22-17
master error address (MEAR) 22-18
MDEU interrupt mask (MDIMR) 22-44
MDEU interrupt status (MDISR) 22-43
MDEU reset control (MDRCR) 22-41
MDEU status (MDSR) 22-41
RNG interrupt mask (RNGIMR) 22-49
RNG interrupt status (RNGISR) 22-48
RNG reset control (RNGRCR) 22-46
RNG status (RNGSR) 22-47
SIU
JTAG device ID (JTAGID) 9-5
module base address (MBAR) 9-2
reset status (RSR) 9-5
SEC sequential access control (SECSACR) 9-4
system breakpoint control (SBCR) 9-3
SRAM
base address (RAMBAR0, RAMBAR1) 7-2
configuration (SSCR) 16-3
TCC, DMA read channel (TCCRDR) 16-5
TCC, DMA write channel (TCCRDW) 16-6
TCC, SEC (TCCRSEC) 16-7
transfer count configuration (TCCR) 16-4
timers
CTM
configuration, fixed timer (CTCRn) 25-4
configuration, variable timer (CTCRn) 25-5
GPT
counter input (GCIRn) 11-5
enable and mode select (GMSn) 11-3
PWM configuration (GPWMn) 11-6
status (GSRn) 11-7
SLT
control (SCRn) 12-2
status (SSRn) 12-4
terminal count (STCNTn) 12-2
timer count (SCNTn) 12-3