Freescale Semiconductor MCF5480 - Manual (Page 832)

MCF548x Reference Manual, Rev. 3
27-14 Freescale Semiconductor
DIRSR Field Descriptions
Bits Name Description
31 TCFE Transfer complete flag interrupt enable. The TCFE bit enables TCF flag in the DSR to generate an
interrupt request.
0 TCF interrupts are disabled
1 TCF interrupts are enabled
30–29 — Reserved, should be cleared.
28 EOQFE End of queue flag interrupt enable. The EOQFE bit enables the EOQF flag in the DSR to generate
an interrupt request.
0 EOQ interrupts are disabled
1 EOQ interrupts are enabled
27 TFUFE Transmit FIFO underflow flag interrupt enable. The TFUFE bit enables the TFUF flag in the DSR to
generate an interrupt request.
0 TFUF interrupts are disabled
1 TFUF interrupts are enabled
26 — Reserved, should be cleared.
25 TFFFE Transmit FIFO fill flag enable.The TFFFE bit enables the TFFF flag in the DSR to generate a
request. The TFFFS bit selects between generating an interrupt request or a DMA request.
0 TFFF interrupts or DMA requests are disabled
1 TFFF interrupts or DMA requests are enabled
24 TFFFS Transmit FIFO fill DMA or interrupt request select. When the TFFF flag bit in the DSR is set, and the
TFFFE bit in the DIRSR register is set, this bit selects between generating an interrupt request or a
DMA request.
0 TFFF flag generates interrupt requests
1 TFFF flag generates DMA requests
23–20 — Reserved, should be cleared.
19 RFOFE Receive FIFO overflow flag interrupt enable. The RFOFE bit enables the RFOF flag in the DSR to
generate an interrupt request.
0 RFOF interrupts are disabled
1 RFOF interrupts are enabled
18 — Reserved, should be cleared
17 RFDFE Receive FIFO drain flag interrupt enable. The RFDFE bit enables the RFDF flag in the DSR to
generate a request. The RFDFS bit selects between generating an interrupt request or a DMA
request.
0 RFDF interrupts are disabled
1 RFDF interrupts are enabled
16 RFDFS Receive FIFO drain DMA or interrupt request select. When the RFDF flag bit in the DSR is set, and
the RFDFE bit in the DIRSR register is set, this bit selects between generating an interrupt request
or a DMA request.
0 RFDF flag generates interrupt requests
1 RFDF flag generates DMA requests
15–0 — Reserved, should be cleared.