Freescale Semiconductor MCF5480 User Manual
Page 657
Advanced Encryption Standard Execution Units (AESU)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
22-55
and the interrupt status register is not updated to reflect the error. If the corresponding bit is not set, then
upon detection of an error, the interrupt status register is updated to reflect the error, causing assertion of
the error interrupt signal, and causing the module to halt processing.
Figure 22-39. AESU Interrupt Mask Register (AESIMR)
describes the AESU interrupt mask register fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ME
AE
OFE
IFE
0
IFO
OFU
0
0
0
0
IE
ERE
CE
KSE
DSE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR 0x32038
Table 22-37. AESIMR Field Descriptions
Bits
Name
Description
31
ME
Mode Error. Indicates that invalid data was written to a register or a reserved mode bit was
set.
0 Mode error enabled
1 Mode error disabled
30
AE
Address Error. An illegal read or write address was detected within the AESU address
space.
1 Address error disabled
0 Address error enabled
29
OFE
Output FIFO Error. The AESU Output FIFO was detected non-empty upon write of AESU
data size register.
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
28
IFE
Input FIFO Error. The AESU Input FIFO was detected non-empty upon generation of done
interrupt.
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
27
—
Reserved
26
IFO
Input FIFO Overflow. The AESU Input FIFO has been pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
25
IFO
Output FIFO Underflow. The AESU Output FIFO has been read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
24–21
—
Reserved