Freescale Semiconductor MCF5480 - Manual (Page 1021)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor Index-7
initiator window 2 base/translation address
(PCIIW2BTAR) 19-19
initiator window configuration (PCIIWCR) 19-19
revision ID/class code (PCICCRIR) 19-9
Rx done counts (PCIRDCR) 19-41
Rx enable (PCIRER) 19-38
Rx FIFO alarm (PCIRFAR) 19-46
Rx FIFO control (PCIRFCR) 19-45
Rx FIFO data (PCIRFDR) 19-43
Rx FIFO status (PCIRFSR) 19-44
Rx FIFO write pointer (PCIRFWPR) 19-47
Rx next address (PCIRNAR) 19-40
Rx packet size (PCIRPSR) 19-36
Rx start address (PCIRSAR) 19-36
Rx status (PCIRSR) 19-42
Rx transaction control (PCIRTCR) 19-37
status/command (PCISCR) 19-7
subsystem ID/subsystem vendor ID (PCISID) 19-12
target base address translation 0 (PCITBATR0) 19-15
target base address translation 1 (PCITBATR1) 19-16
target control (PCITCR) 19-16
Tx done counts (PCITDCR) 19-28
Tx enable (PCITER) 19-26
Tx FIFO alarm (PCITFAR) 19-33
Tx FIFO control (PCITFCR) 19-32, 19-33
Tx FIFO data (PCITFDR) 19-31
Tx FIFO read pointer (PCITFRPR) 19-34
Tx FIFO status (PCITFSR) 19-31, 19-32, 19-33
Tx FIFO write pointer (PCITFWPR) 19-35
Tx last word register (PCITLWR) 19-28
Tx next address (PCITNAR) 19-27
Tx packet size (PCITPSR) 19-23
Tx start address (PCITSAR) 19-24
Tx status (PCITSR) 19-29
Tx transaction control (PCITTCR) 19-25
signals
clock (CLKIN) 19-3
frame (PCIFRAME) 19-3
parity error (PCIPERR) 19-3
stop (PCISTOP) 19-3
Program counter 3-9
PSC
baud rate calculation 26-21
block diagram 26-1
interrrupts 26-48
memory map 26-3
modes
AC97 26-39, 26-51
FIR 26-42, 26-54
clock divide ratio 26-27
MIR 26-41, 26-53
modem16 26-38, 26-51
modem8 26-37, 26-50
multidrop 26-36
SIR 26-41, 26-52
UART 26-35, 26-49
automatic echo 26-46
local loopback 26-46
remote loopback 26-47
registers
auxiliary control (PSCACRn) 26-18
clock select (PSCCSRn) 26-10
command (PSCCRn) 26-11
counter timer (PSCCTURn, PSCCTLRn) 26-21
infrared control 1 (PSCIRCR1n) 26-24
infrared control 2 (PSCIRCR2n) 26-24
infrared FIR divide (PSCIRFDRn) 26-26
infrared MIR divide (PSCIRMDRn) 26-25
infrared SIR divide (PSCIRSDRn) 26-25
input port (PSCIP) 26-21
input port (PSCIPn) 26-21
input port change (PSCIPCRn) 26-17
interrupt mask (PSCIMRn) 26-19
interrupt status (PSCISRn) 26-18
mode 1 (PSCMR1) 26-5
mode 1 (PSCMR1n) 26-5
mode 2 (PSCMR2n) 26-6
output port bit reset (PSCOPRESETn) 26-22
output port bit set (PSCOPSETn) 26-22
PSC/IrDA control (PSCSICRn) 26-23
receiver and transmitter buffer (PSCRBn,
PSCTBn) 26-14
RxFIFO and TxFIFO alarm (PSCRFARn,
PSCTFARn) 26-32
RxFIFO and TxFIFO control (PSCRFCRn,
PSCTFCRn) 26-30
RxFIFO and TxFIFO counter (PSCRFCRn,
PSCTFCRn) 26-27
RxFIFO and TxFIFO data (PSCRFDRn,
PSCTFDRn) 26-27
RxFIFO and TxFIFO last read frame pointer
(PSCRLRFPn, PSCTLRFPn) 26-33
RxFIFO and TxFIFO last write frame pointer
(PSCRLWFPn, PSCTLWFPn) 26-34
RxFIFO and TxFIFO read pointer (PSCRFRPn,
PSCTFRPn) 26-32
RxFIFO and TxFIFO status (PSCRFSRn,
PSCTFSRn) 26-28
RxFIFO and TxFIFO write pointer (PSCRFWPn,
PSCTFWPn) 26-33
status (PSCSRn) 26-8
reset 26-47