Freescale Semiconductor MCF5480 - Manual (Page 568)

MCF548x Reference Manual, Rev. 3
20-8 Freescale Semiconductor
Figure 20-5. Alternating Priority
Device 0 and device 1 assert REQ while the bus is parked with device 2. Because the PCI bus is idle, the
arbiter deasserts GNT to the parked master (device 2) and a cycle later, grants access to device 0. Device
0’s transaction begins when PCIFRAME is asserted on clock 4. (The earliest device 0 can initiate a
transaction on the PCI bus is the cycle following GNT assertion.) It leaves its REQ asserted to indicate it
wants to perform another transaction. When PCIFRAME is asserted (PCI bus is active), hidden arbitration
occurs and GNT to device 0 deasserts on the same cycle the arbiter asserts GNT to device 1. (Device 1 has
priority because, of the two requesting masters, device 0 and device 1, device 1 is the least recently used.)
Device 0 completes its transaction on clock 5 and relinquishes the PCI bus. On clock 6, device 1 detects
the PCI bus is idle (PCIFRAME and PCIIRDY deasserted) and because its GNT is still asserted, initiates
the next transaction in the next cycle. To indicate it only requires this single transaction on the PCI bus,
device 1 deasserts REQ on the same cycle it asserts PCIFRAME.
Because device 0 is the only other requesting device, the arbiter asserts its GNT and will leave its GNT
asserted until another request is detected.
Figure 20-6 starts out just like Figure 20-5 with the bus parked with device 2 and both device 0 and device
1 requesting use of the PCI bus. (Assume device 0, device 1, and device 2 are assigned the same priority
group and no other masters are requesting use of the bus.)
PCI_CLK
REQ[0]
REQ[1]
REQ[2]
GNT[0]
GNT[1]
PCIIRDY
PCIFRAME
PCIAD
0 1 2 3 4 5 6 7 8 9 10 11 12
GNT[2]
DRIVEN LOW ADDR DATA ADDR DATA ADDR DATA
Access 0 Access 1 Access 0
STATE IDLE GRANT ACTIVE GRANT ACTIVE GRANT ACTIVE TURN
(Parked)