Freescale Semiconductor MCF5480 - Manual (Page 63)

MCF548x Family Features
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 1-5
— Execution units for the following:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random number generator compliant with FIPS 140-1 standards for randomness and
non-determinism
— Dual-channel architecture permits single-pass encryption and authentication
• 32-Kbyte system SRAM
— Arbitration mechanism shares bandwidth between internal bus masters (CPU, cryptography
accelerator, PCI, and DMA)
• System integration unit (SIU)
— Interrupt controller
— Watchdog timer
— Two 32-bit slice timers for periodic alarm and interrupt generation
— Up to four 32-bit general-purpose timers with capture, compare, and PWM capability
— General-purpose I/O ports multiplexed with peripheral pins
• Debug and test features
— Core debug support via ColdFire background debug mode (BDM) port
— Chip debug support via JTAG/ IEEE 1149.1 test access port
• PLL and clock generator
— 30–66.67 MHz input frequency range
• Operating Voltages
— 1.5V internal logic
— 2.5V DDR SDRAM bus I/O (1.25V V
REF
)
— 3.3V PCI, FlexBus, and all other I/O
• Estimated power consumption
— <1.5W
1.4.1 ColdFire V4e Core Overview
The ColdFire V4e core is a variable-length RISC, clock-multiplied core that includes a Harvard memory
architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue capabilities.
The limited superscalar design approaches dual-issue performance with the cost of a scalar execution
pipeline.
The ColdFire V4e processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The four-stage instruction fetch pipeline (IFP) prefetches the instruction stream,
examines it to predict changes of flow, partially decodes instructions, and packages fetched data into
instructions for the operand execution pipeline (OEP). The IFP can prefetch instructions before the OEP
needs them, minimizing the wait for instructions. The instruction buffer is a 10 instruction, first-in-first-out
(FIFO) buffer that decouples the IFP and OEP by holding prefetched instructions awaiting execution in
the OEP. The OEP includes five pipeline stages: the first stage decodes instructions and selects operands
(DS), and the second stage generates operand addresses (OAG). The third and fourth stages fetch operands
(OC1 and OC2), and the fifth stage executes instructions (EX).