Freescale Semiconductor MCF5480 - Manual (Page 10)

MCF548x Reference Manual, Rev. 3
x Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
3.7.4 Miscellaneous Instruction Execution Timing ........................................................... 3-32
3.7.5 Branch Instruction Execution Timing ....................................................................... 3-33
3.7.6 EMAC Instruction Execution Times ........................................................................ 3-34
3.7.7 FPU Instruction Execution Times ............................................................................. 3-35
3.8 Exception Processing Overview ................................................................................... 3-36
3.8.1 Exception Stack Frame Definition ............................................................................ 3-38
3.8.2 Processor Exceptions ................................................................................................ 3-39
3.9 Precise Faults ................................................................................................................ 3-42
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1 Introduction ..................................................................................................................... 4-1
4.1.1 MAC Overview ........................................................................................................... 4-2
4.1.2 General Operation ....................................................................................................... 4-2
4.2 Memory Map/Register Definition .................................................................................. 4-5
4.2.1 MAC Status Register (MACSR) ................................................................................. 4-5
4.2.1.1 Fractional Operation Mode ..................................................................................... 4-8
4.2.2 Mask Register (MASK) ............................................................................................ 4-10
4.3 EMAC Instruction Set Summary .................................................................................. 4-11
4.3.1 EMAC Instruction Execution Timing ....................................................................... 4-11
4.3.2 Data Representation .................................................................................................. 4-12
4.3.3 EMAC Opcodes ........................................................................................................ 4-13
Chapter 5
Memory Management Unit (MMU)
5.1 Features ........................................................................................................................... 5-1
5.2 Virtual Memory Management Architecture ................................................................... 5-1
5.2.1 MMU Architecture Features ....................................................................................... 5-1
5.2.2 MMU Architecture Location ...................................................................................... 5-2
5.2.3 MMU Architecture Implementation ........................................................................... 5-3
5.2.3.1 Precise Faults .......................................................................................................... 5-4
5.2.3.2 MMU Access .......................................................................................................... 5-4
5.2.3.3 Virtual Mode ........................................................................................................... 5-4
5.2.3.4 Virtual Memory References ................................................................................... 5-4
5.2.3.5 Instruction and Data Cache Addresses ................................................................... 5-4
5.2.3.6 Supervisor/User Stack Pointers .............................................................................. 5-5
5.2.3.7 Access Error Stack Frame ...................................................................................... 5-5
5.2.3.8 Expanded Control Register Space .......................................................................... 5-5