Freescale Semiconductor MCF5480 - Manual (Page 34)

MCF548x Reference Manual, Rev. 3
xxxiv Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
27.7.2.4 Tx FIFO Buffering Mechanism .......................................................................... 27-21
27.7.2.5 Rx FIFO Buffering Mechanism .......................................................................... 27-22
27.7.3 DSPI Baud Rate and Clock Delay Generation ....................................................... 27-22
27.7.3.1 Baud Rate Generator ........................................................................................... 27-23
27.7.3.2 CS to SCK Delay (tCSC) .................................................................................... 27-23
27.7.3.3 After DSPISCK Delay (tASC) ........................................................................... 27-23
27.7.3.4 Delay after Transfer (t
DT
) ................................................................................... 27-23
27.7.3.5 Peripheral Chip Select Strobe Enable (PCSS) .................................................... 27-24
27.7.4 Transfer Formats ..................................................................................................... 27-25
27.7.4.1 Classic SPI Transfer Format (CPHA = 0) .......................................................... 27-25
27.7.4.2 Classic SPI Transfer Format (CPHA = 1) .......................................................... 27-26
27.7.4.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0) .................................... 27-27
27.7.4.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) .................................... 27-28
27.7.4.5 Continuous Selection Format ............................................................................. 27-29
27.7.5 Continuous Serial Communications Clock ............................................................. 27-30
27.7.6 Interrupts/DMA Requests ....................................................................................... 27-31
27.7.6.1 End of Queue Interrupt Request ......................................................................... 27-32
27.7.6.2 Transmit FIFO Fill Interrupt or DMA Request .................................................. 27-32
27.7.6.3 Transfer Complete Interrupt Request ................................................................. 27-32
27.7.6.4 Transmit FIFO Underflow Interrupt Request ..................................................... 27-32
27.7.6.5 Receive FIFO Drain Interrupt or DMA Request ................................................ 27-32
27.7.6.6 Receive FIFO Overflow Interrupt Request ......................................................... 27-32
27.8 Initialization and Application Information ................................................................. 27-33
27.8.1 How to Change Queues .......................................................................................... 27-33
27.8.2 Baud Rate Settings .................................................................................................. 27-33
27.8.3 Delay Settings ......................................................................................................... 27-34
27.8.4 Calculation of FIFO Pointer Addresses .................................................................. 27-35
27.8.4.1 Address Calculation for the First-in Entry and Last-in Entry in the Tx FIFO ... 27-36
27.8.4.2 Address Calculation for the First-in Entry and Last-in Entry in the Rx FIFO ... 27-36
Chapter 28
I
2
C Interface
28.1 Introduction ................................................................................................................... 28-1
28.1.1 Block Diagram .......................................................................................................... 28-1
28.1.2 I2C Overview ............................................................................................................ 28-2
28.1.3 Features ..................................................................................................................... 28-2
28.2 External Signals ............................................................................................................ 28-2
28.3 Memory Map/Register Definition ................................................................................ 28-3
28.3.1 I2C Register Map ...................................................................................................... 28-3
28.3.2 Register Descriptions ................................................................................................ 28-3