Freescale Semiconductor MCF5480 - Manual (Page 22)

MCF548x Reference Manual, Rev. 3
xxii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
19.3.2.2 Target Base Address Translation Register 0 (PCITBATR0) ............................. 19-15
19.3.2.3 Target Base Address Translation Register 1 (PCITBATR1) ............................. 19-16
19.3.2.4 Target Control Register (PCITCR) ..................................................................... 19-16
19.3.2.5 Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR) ......... 19-17
19.3.2.6 Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR) ......... 19-18
19.3.2.7 Initiator Window 2 Base/Translation Address Register (PCIIW2BTAR) ......... 19-19
19.3.2.8 Initiator Window Configuration Register (PCIIWCR) ....................................... 19-19
19.3.2.9 Initiator Control Register (PCIICR) ................................................................... 19-20
19.3.2.10 Initiator Status Register (PCIISR) ...................................................................... 19-21
19.3.2.11 Configuration Address Register (PCICAR) ....................................................... 19-22
19.3.3 Communication Subsystem Interface Registers ..................................................... 19-23
19.3.3.1 Comm Bus FIFO Transmit Interface .................................................................. 19-23
19.3.3.2 Comm Bus FIFO Receive Interface ................................................................... 19-35
19.4 Functional Description ................................................................................................ 19-48
19.4.1 PCI Bus Protocol .................................................................................................... 19-48
19.4.1.1 PCI Bus Background .......................................................................................... 19-48
19.4.1.2 Basic Transfer Control ........................................................................................ 19-49
19.4.1.3 PCI Transactions ................................................................................................. 19-49
19.4.1.4 PCI Bus Commands ............................................................................................ 19-51
19.4.1.5 Addressing .......................................................................................................... 19-52
19.4.2 Initiator Arbitration ................................................................................................. 19-55
19.4.2.1 Priority Scheme .................................................................................................. 19-56
19.4.3 Configuration Interface ........................................................................................... 19-56
19.4.4 XL Bus Initiator Interface ....................................................................................... 19-56
19.4.4.1 Endian Translation .............................................................................................. 19-58
19.4.4.2 Configuration Mechanism .................................................................................. 19-60
19.4.4.3 Interrupt Acknowledge Transactions .................................................................. 19-62
19.4.4.4 Special Cycle Transactions ................................................................................. 19-62
19.4.4.5 Transaction Termination ..................................................................................... 19-63
19.4.5 XL Bus Target Interface ........................................................................................ 19-63
19.4.5.1 Reads from Local Memory ................................................................................. 19-64
19.4.5.2 Local Memory Writes ......................................................................................... 19-64
19.4.5.3 Data Translation .................................................................................................. 19-64
19.4.5.4 Target Abort ........................................................................................................ 19-66
19.4.5.5 Latrule Disable .................................................................................................... 19-66
19.4.6 Communication Subsystem Initiator Interface ....................................................... 19-66
19.4.6.1 Access Width ...................................................................................................... 19-67
19.4.6.2 Addressing .......................................................................................................... 19-67
19.4.6.3 Data Translation .................................................................................................. 19-68
19.4.6.4 Initialization ........................................................................................................ 19-68
19.4.6.5 Restart and Reset ................................................................................................ 19-68