Freescale Semiconductor MCF5480 - Manual (Page 917)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 29-43
26-24 GR Granularity. The functionality of this field depends on the direction of the FIFO. The direction, type,
and packet size are defined in the EPnSTAT registers.
For Transmitter (IN): These bits control the high “watermark” point at which the FIFO will negate its
alarm condition (i.e. request for data). It represents the number of Free Bytes multiplied by 4. For
example, if GR = 000, the FIFO will wait to become completely full before it stops requesting data. If
GR = 001, the FIFO will stop requesting data when it has only one longword of space remaining.
For Receiver (OUT): These bits control the high “watermark” point at which the FIFO will negate its
alarm condition (i.e. its request to empty its data). It represents the number of Data Bytes multiplied
by 4. For example, if GR = 001, the FIFO will stop requesting service when it has only one longword
of data remaining
23 IPMSK When set, this bit masks the IP bit in the EPnFSR register from generating a FIFO error.
0 IP status assertion will cause EPnISR[ERR] assertion.
1 IP status assertion will not cause EPnISR[ERR] assertion.
22 FAEMSK When set, this bit masks the FAE bit in the EPnFSR register from generating a FIFO error.
0 FAE status assertion will cause EPnISR[ERR] assertion.
1 FAE status assertion will not cause EPnISR[ERR] assertion.
21 RXWMSK When set, this bit masks the RXW bit in the EPnFSR register from generating a FIFO error.
0 RXW status assertion will cause EPnISR[ERR] assertion.
1 RXW status assertion will not cause EPnISR[ERR] assertion.
20 UFMSK When set, this bit masks the UF bit in the EPnFSR register from generating a FIFO error.
0 UF status assertion will cause EPnISR[ERR] assertion.
1 UF status assertion will not cause EPnISR[ERR] assertion.
19 OFMSK When set, this bit masks the OF bit in the EPnFSR register from generating a FIFO error.
0 OF status assertion will cause EPnISR[ERR] assertion.
1 OF status assertion will not cause EPnISR[ERR] assertion.
18 TXWMSK When set, this bit masks the TXW bit in the EPnFSR register from generating a FIFO error.
0 TXW status assertion will cause EPnISR[ERR] assertion.
1 TXW status assertion will not cause EPnISR[ERR] assertion.
17–16 — Reserved, should be cleared.
15–0 CTR Counter. When in timer mode, the value of COUNTER[15:0] is multiplied by 64 and that result is used
to determine the number of cycles that should elapse before the frame ready service request is
asserted.
Table 29-42. EPnFCR Field Descriptions (Continued)
Bits Name Description