MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
vii
Contents
Paragraph
Number
Title
Page
Number
2.2.5.1
Reset In (RSTI) ..................................................................................................... 2-22
2.2.5.2
Reset Out (RSTO) ................................................................................................. 2-22
2.2.5.3
Clock In (CLKIN) ................................................................................................. 2-22
2.2.6
Reset Configuration Pins .......................................................................................... 2-22
2.2.6.1
AD[12:8]—CLKIN to SDCLK Ratio (CLKCONFIG[4:0]) ................................ 2-22
2.2.6.2
AD5—FlexBus Size Configuration (FBSIZE) ..................................................... 2-23
2.2.6.3
AD4—32-bit FlexBus Configuration (FBMODE) ............................................... 2-23
2.2.6.4
AD3—Byte Enable Configuration (BECONFIG) ................................................ 2-23
2.2.6.5
AD2—Auto Acknowledge Configuration (AACONFIG) .................................... 2-24
2.2.6.6
AD[1:0]—Port Size Configuration (PSCONFIG) ................................................ 2-24
2.2.7
Ethernet Module Signals ........................................................................................... 2-24
2.2.7.1
Management Data (E0MDIO, E1MDIO) ............................................................. 2-24
2.2.7.2
Management Data Clock (E0MDC, E1MDC) ...................................................... 2-25
2.2.7.3
Transmit Clock (E0TXCLK, E1TXCLK) ............................................................ 2-25
2.2.7.4
Transmit Enable (E0TXEN, E1TXEN) ................................................................ 2-25
2.2.7.5
Transmit Data 0 (E0TXD0, E1TXD0) ................................................................. 2-25
2.2.7.6
Collision (E0COL, E1COL) ................................................................................. 2-25
2.2.7.7
Receive Clock (E0RXCLK, E1RXCLK) ............................................................. 2-25
2.2.7.8
Receive Data Valid (E0RXDV, E1RXDV) .......................................................... 2-25
2.2.7.9
Receive Data 0 (E0RXD0, E1RXD0) .................................................................. 2-25
2.2.7.10
Carrier Receive Sense (E0CRS, E1CRS) ............................................................. 2-25
2.2.7.11
Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) .................................................. 2-25
2.2.7.12
Transmit Error (E0TXER, E1TXER) ................................................................... 2-26
2.2.7.13
Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1]) ................................................... 2-26
2.2.7.14
Receive Error (E0RXER, E1RXER) .................................................................... 2-26
2.2.8
Universal Serial Bus (USB) ...................................................................................... 2-26
2.2.8.1
USB Differential Data (USBD+, USBD–) ........................................................... 2-26
2.2.8.2
USBVBUS ............................................................................................................ 2-26
2.2.8.3
USBRBIAS ........................................................................................................... 2-26
2.2.8.4
USBCLKIN .......................................................................................................... 2-26
2.2.8.5
USBCLKOUT ...................................................................................................... 2-26
2.2.9
DMA Serial Peripheral Interface (DSPI) Signals ..................................................... 2-26
2.2.9.1
DSPI Synchronous Serial Data Output (DSPISOUT) .......................................... 2-26
2.2.9.2
DSPI Synchronous Serial Data Input (DSPISIN) ................................................. 2-27
2.2.9.3
DSPI Serial Clock (DSPISCK) ............................................................................. 2-27
2.2.9.4
DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 2-27
2.2.9.5
DSPI Chip Selects (DSPICS[2:3]) ........................................................................ 2-27
2.2.9.6
DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 2-27
2.2.10
FlexCAN Signals ...................................................................................................... 2-27
2.2.10.1
FlexCAN Transmit (CANTX0, CANTX1) .......................................................... 2-27
2.2.10.2
FlexCAN Receive (CANRX0, CANRX1) ........................................................... 2-27