Freescale Semiconductor MCF5480 - Manual (Page 577)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 21-7
Table 21-2. CANMCR Field Descriptions
Bits Name Description
31 MDIS Module disable. This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts
down the FlexCAN clocks. This is the only bit in CANMCR not affected by soft reset. See
Section 21.1.4.3, “Module Disabled Mode ” for more information.
0 Enable the FlexCAN module, clocks enabled
1 Disable the FlexCAN module, clocks disabled
30 FRZ FREEZE assertion response. When FRZ = 1, the FlexCAN can enter debug mode when the BKPT
line is asserted or the HALT bit is set. Clearing this bit field causes the FlexCAN to exit debug mode.
Refer to
Section 21.1.4.2, “Freeze Mode ” for more information.
0 FlexCAN ignores the BKPT signal and the HALT bit in the module configuration register.
1 FlexCAN module enabled to enter debug mode.
29 — Reserved, should be cleared.
28 HALT Halt FlexCAN S-Clock. Setting the HALT bit has the same effect as assertion of the BKPT signal on
the FlexCAN without requiring that BKPT be asserted, i.e., it puts the FlexCAN module into freeze
mode. This bit is set to one after reset. It should be cleared after initializing the message buffers and
control registers. FlexCAN message buffer receive and transmit functions are inactive until this bit is
cleared. While in debug mode, the CPU has write access to the error counter register, that is
otherwise read-only.
When HALT is set, write access to certain registers and bits that are normally read-only is allowed.
0 The FlexCAN operates normally
1 FlexCAN enters debug mode if FRZ = 1
27–26 — Reserved, should be cleared.
25 SOFTRST Soft reset. When this bit is set, the FlexCAN resets its internal state machines (sequencer, error
counters, error flags, and timer) and the host interface registers (CANMCR [except the MDIS bit],
TIMER, ERRCNT, ERRSTAT, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed (CANCTRL,
RXGMASK, RX14MASK, RX15MASK). Message buffers are also not changed. This allows
SOFTRST to be used as a debug feature while the system is running.
After setting SOFTRST, allow one complete bus cycle to elapse for the internal FlexCAN circuitry to
completely reset before executing another access to CANMCR.
The FlexCAN clears this bit once the internal reset cycle is completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
24 FRZACK FlexCAN disable. When the FlexCAN enters freeze mode, it sets the FRZACK bit. This bit should be
polled to determine if the FlexCAN has entered freeze mode. When freeze mode is exited, this bit is
negated once the FlexCAN prescaler is enabled. This is a read-only bit.
0 The FlexCAN has exited debug mode and the prescaler is enabled.
1 The FlexCAN has entered debug mode, and the prescaler is disabled.
23 SUPV Supervisor/user data space. The SUPV bit places the FlexCAN registers in either supervisor or user
data space.
0 Registers with access controlled by the SUPV bit are accessible in either user or supervisor
privilege mode.
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode.