Freescale Semiconductor MCF5480 - Manual (Page 1023)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor Index-9
PCI grant pin assignment (PAR_PCIBG) 15-25
PCI request pin assignment (PAR_PCIBR) 15-26
port clear output data (PCLRR_x) 15-18–15-20
port x data direction (PDDR_x) 15-11–15-14
port x output data (PODR_x) 15-8–15-11
port x pin assignment (PAR_x) 15-21
port x pin data/set data (PPDSDR_x) 15-14–15-17
PSC0 pin assignment (PAR_PSC0) 15-29
PSC1 pin assignment (PAR_PSC1) 15-28
PSC2 pin assignment (PAR_PSC2) 15-28
PSC3 pin assignment (PAR_PSC3) 15-27
I
2
C
address (I2AR) 28-3
control (I2CR) 28-5
data I/O (I2DR) 28-7
frequency divider (I2FDR) 28-4
interrupt control (I2ICR) 28-7
status (I2SR) 28-5
interrupt controller
interrupt acknowledge level and priority
(IACKLPRn) 13-10
interrupt control (ICRnx) 13-11
interrupt force high/low (INTFRCHn,
INTFRCLn) 13-8
interrupt pending high/low (IPRHn, IPRLn) 13-5
interrupt request level (IRLRn) 13-10
level n IACK (LnIACK) 13-13
mask high/low (IMRHn, n) 13-7
software IACK (SWIACKR) 13-13
JTAG
boundary scan 23-6
bypass 23-5
IDCODE 23-4
instruction shift (IR) 23-4
JTAG_CFM_CLKDIV 23-5
TEST_CTRL 23-5
MMU
base address (MMUBAR) 5-5, 5-10
control (MMUCR) 5-11
fault, test, or TLB address (MMUAR) 5-15
operation (MMUOR) 5-12
read/write tag and data entry (MMUTR,
MMUDR) 5-16
status (MMUSR) 5-14
PCI arbiter
control (PACR) 20-3
PCI controller
base address 0 (PCIBAR0) 19-11
base address 1 (PCIBAR1) 19-12
cardbus CIS pointer (PCICCPR) 19-12
configuration 1 (PCICR1) 19-10
configuration 2 (PCICR2) 19-13
configuration address (PCICAR) 19-22
device ID/vendor ID (PCIIDR) 19-7
global status/control (PCIGSCR) 19-14
initiator control (PCIICR) 19-20
initiator status (PCIISR) 19-21
initiator window 0 base/translation address
(PCIIW0BTAR) 19-17
initiator window 1 base/translation address
(PCIIW1BTAR) 19-18
initiator window 2 base/translation address
(PCIIW2BTAR) 19-19
initiator window configuration (PCIIWCR) 19-19
revision ID/class code (PCICCRIR) 19-9
Rx done counts (PCIRDCR) 19-41
Rx enable (PCIRER) 19-38
Rx FIFO (PCIRFDR) 19-43
Rx FIFO alarm (PCIRFAR) 19-46
Rx FIFO control (PCIRFCR) 19-45
Rx FIFO status (PCIRFSR) 19-44
Rx FIFO write pointer (PCIRFWPR) 19-47
Rx next address (PCIRNAR) 19-40
Rx packet size (PCIRPSR) 19-36
Rx start address (PCIRSAR) 19-36
Rx status (PCIRSR) 19-42
Rx transaction control (PCIRTCR) 19-37
status/command (PCISCR) 19-7
subsystem ID/subsystem vendor ID (PCISID) 19-12
target base address translation 0 (PCITBATR0) 19-15
target base address translation 1 (PCITBATR1) 19-16
target control (PCITCR) 19-16
Tx done counts (PCITDCR) 19-28
Tx enable (PCITER) 19-26
Tx FIFO alarm (PCITFAR) 19-33
Tx FIFO control (PCITFCR) 19-32, 19-33
Tx FIFO data (PCITFDR) 19-31
Tx FIFO read pointer (PCITFRPR) 19-34
Tx FIFO status (PCITFSR) 19-31, 19-32, 19-33
Tx FIFO write pointer (PCITFWPR) 19-35
Tx last word register (PCITLWR) 19-28
Tx next address (PCITNAR) 19-27
Tx packet size (PCITPSR) 19-23
Tx start address (PCITSAR) 19-24
Tx status (PCITSR) 19-29
Tx transaction control (PCITTCR) 19-25
programming model table 3-13
PSC
auxiliary control (PSCACRn) 26-18
clock select (PSCCSRn) 26-10
command (PSCCRn) 26-11
counter timer (PSCCTURn, PSCCTLRn) 26-21
infrared control 1 (PSCIRCR1n) 26-24
infrared control 2 (PSCIRCR2n) 26-24