Freescale Semiconductor MCF5480 User Manual
Page 183
MMU Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
5-17
MMUDR,
, contains the physical address, page size, cache mode field, supervisor-protect bit,
read, write, execute permission bits, and lock-entry bit.
describes MMUDR fields.
1
SG
Shared global. Indicates when the entry is shared among user address spaces. If an entry
is shared, its ASID is not part of the TLB hit determination for user accesses.
0 This entry is not shared globally.
1 This entry is shared globally.
Note that the ASID can be used to determine supervisor mode hits to allow two sharing
levels. If SG and MMUCR[ASM] are set and the ASID is not zero, all users (but not the
supervisor) share an entry. If SG and MMUCR[ASM] are set and the ASID is zero, all users
and the supervisor share an entry. The description of ASM in
details supervisor
mode and ASID compares.
0
V
Valid. Indicates when the entry is valid. Only valid entries generate a TLB hit.
0 Entry is not valid.
1 Entry is valid.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
PA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PA
SZ
CM
SP
R
W
X
LK
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MMUBAR + 0x014
Figure 5-9. MMU Read/Write TLB Data Register (MMUDR)
Table 5-10. MMUDR Field Descriptions
Bits
Name
Descriptions
31–10
PA
Physical address. Defines the physical address which is mapped by this entry. The number
of bits used to build the effective physical address if this TLB entry hits depends on the
page size field.
9–8
SZ
Page size. Page size for this entry:
00 1 Mbyte: VA[31–20] used for TLB hit
01 4 Kbytes VA[31–12] used for TLB hit
10 8 Kbytes VA[31–13] used for TLB hit
11 1 Kbyte VA[31–10] used for TLB hit
Table 5-9. MMUTR Field Descriptions (Continued)
Bits
Name
Description