Freescale Semiconductor MCF5480 - Manual (Page 616)

MCF548x Reference Manual, Rev. 3
22-14 Freescale Semiconductor
22.6.4.3 SEC Interrupt Mask Registers (SIMRH and SIMRL)
The SEC generates a single interrupt output from all possible interrupt sources. These sources can be
masked by the SIMR registers. If unmasked, the interrupt source value, when active, is captured into the
SEC interrupt status registers (SISRH and SISRL). Figure 22-11 and Figure 22-12 show the bit positions
of each potential interrupt source. Each interrupt source is individually masked by setting it’s
corresponding bit.
22.6.4.4 SEC Interrupt Status Registers (SISRH and SISRL)
The SEC interrupt status registers contain fields representing all possible sources of interrupts. The SISR
is cleared either by a reset, or by writing the appropriate bits active in the SEC interrupt control registers
(SICRH and SICRL). Figure 22-11 and Figure 22-12 shows the bit positions of each potential interrupt
source.
22.6.4.5 SEC Interrupt Control Registers (SICRH and SICRL)
The SEC interrupt control registers (SICRH and SICRL) provide a means of clearing the SISR registers.
When a bit in either SICR is written with a 1, the corresponding bit in the SISR is cleared, clearing the
interrupt output pin IRQ (assuming the cleared bit in the SISR is the only interrupt source). If the input
source to the SISR is a steady-state signal that remains active, the appropriate SISR bit, and subsequently
IRQ, will be reasserted shortly thereafter. The complete bit definitions for the SICR can be found in
Figure 22-11 and Figure 22-12 .
When an SICR bit is written, it will automatically clear itself one cycle later. That is, it is not necessary to
write a 0 to a bit position which has been written with a 1.
NOTE
Interrupts are registered and sent based upon the conditions which cause
them. If the cause of an interrupt is not removed, the interrupt will return a
few cycles after it has been cleared using the SICR.
Table 22-6. EUASRH and EUASRL Field Descriptions
Bits Name Description
31–0 See Figure 22-10 Channel Assignment. Each field corresponds to one of the SEC EUs. The field indicates if
the EU is currently assigned to one of the two channels as shown in
Table 22-5 .