Freescale Semiconductor MCF5480 User Manual
Page 541
Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-57
The particular type of PCI transaction generated is determined by the PCI configuration bits associated
with the address window (PCIIWCR). For example, the user might set one window to do PCI memory read
multiple accesses, one window for PCI I/O accesses, and the other window to do non-prefetchable
(memory-mapped I/O) PCI memory accesses. See
for command translations.
In addition to the configurable address window mapping logic, the register interface provides a
configuration address register, which provides the ability to generate configuration, interrupt
acknowledge, and special cycles. External PCI devices should be configured through this interface. See
Section 19.4.4.2, “Configuration Mechanism
” for configuration, interrupt acknowledge, and special cycle
command support.
The PCI XL bus initiator interface supports all XL bus transactions, including single-beat transfers and
bursts (32 bytes). Single-beat 64-bit data transactions are automatically translated into 2-beat burst
transfers on the PCI bus.
Standard XL bus burst transactions are supported as well, however, buffering is implemented to boost
performance during writes and avoid deadlock scenario for all reads and memory writes. If the target for
an XL bus read from PCI disconnects part way through the burst, the MCF548may have to handle a local
memory access from an alternate PCI master before the disconnected transfer can continue.
XL bus initiator read requests are decoded into four types: PCI Memory, I/O, Configuration, and Interrupt
Acknowledge. The PCI Controller must first gain access to the PCI bus before acknowledging the XL bus
read request. The specific timing of the address acknowledge is dependent upon the type of transfer.
When the XL bus requests burst data from PCI space, the data received from PCI is stored in a 32-byte
read buffer. The PCI Controller does not terminate the address tenure of the XL bus transaction until all
requested data is latched. This is because PCI targets are allowed to disconnect in the middle of a transfer,
and the XL bus requires burst transfers to be atomic. If the PCI target disconnects in the middle of the data
transfer and an alternate PCI master acquires the bus and initiates a local memory access, the Controller
retries the internal read transaction on the XL bus. The PCI Controller continues to request mastership of
the PCI bus until the original request is completed.
For example, if the XL bus initiates a burst read, and the PCI target disconnects after transferring the first
half of the burst, the MCF548x re-arbitrates for the PCI bus, and when granted, initiates a new transaction
with the address of the third beat of the burst (4-beat XL bus bursts). If an alternate PCI master requests
data from local memory while the PCI Controller is waiting for the PCI bus grant, the PCI controller retries
the XL bus transaction to allow the PCI-initiated transaction to complete and the read buffer will be
emptied. Transactions are not reordered, but taken first come, first served.
When the MCF548x is acting as in initiator/master, PCI critical-word-first (CWF) burst operation (i.e.
cache line wrap burst) is supported, and the 2-bit cache line wrap address mode is driven on the address
bus when the XL bus starts the burst at a non-zero-word-first address. Note that this option is only provided
as a means for the initiator to support memory targets that support cache-line wrap. The processor is not
permitted to cache from memory targets residing on the PCI bus in the 2.2 spec.
XL bus writes are decoded into PCI memory, PCI I/O, PCI configuration, or special cycles. If the
transaction decodes into an I/O, configuration, or special cycle, the write is connected. The PCI controller
gains access to the PCI bus and successfully transfers the data before it asserts address acknowledge to the
XL bus. If the address maps to PCI memory space, the XL bus address tenure is immediately
acknowledged and write data is posted.
A 32-byte write buffer is used to post memory writes from XL bus to PCI. Buffering minimizes the effect
of the slower PCI bus on the higher-speed XL bus. It may contain single-beat XL bus write transactions or
a single burst. After the XL bus write data is latched internally, the bus is available for subsequent
transactions without having to wait for the write to the PCI target to complete. If a subsequent XL bus write