Freescale Semiconductor MCF5480 - Manual (Page 19)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xix
Contents
Paragraph
Number
Title
Page
Number
17.5.1.2 Global Chip-Select Operation ............................................................................... 17-6
17.5.2 Chip-Select Registers ................................................................................................ 17-7
17.5.2.1 Chip-Select Address Registers (CSAR0–CSAR5) ............................................... 17-8
17.5.2.2 Chip-Select Mask Registers (CSMR0–CSMR5) .................................................. 17-9
17.5.2.3 Chip-Select Control Registers (CSCR0–CSCR5) .............................................. 17-10
17.6 Functional Description ................................................................................................ 17-12
17.6.1 Data Transfer Operation ......................................................................................... 17-12
17.6.2 Data Byte Alignment and Physical Connections .................................................... 17-12
17.6.3 Address/Data Bus Multiplexing .............................................................................. 17-13
17.6.4 Bus Cycle Execution ............................................................................................... 17-13
17.6.4.1 Data Transfer Cycle States ................................................................................. 17-14
17.6.5 FlexBus Timing Examples ...................................................................................... 17-15
17.6.5.1 Basic Read Bus Cycle ......................................................................................... 17-15
17.6.5.2 Basic Write Bus Cycle ........................................................................................ 17-16
17.6.5.3 Bus Cycle Multiplexing ...................................................................................... 17-17
17.6.5.4 Timing Variations ............................................................................................... 17-21
17.6.6 Burst Cycles ............................................................................................................ 17-26
17.6.7 Misaligned Operands .............................................................................................. 17-31
17.6.8 Bus Errors ............................................................................................................... 17-32
Chapter 18
SDRAM Controller (SDRAMC)
18.1 Introduction ................................................................................................................... 18-1
18.2 Overview ....................................................................................................................... 18-1
18.2.1 Features ..................................................................................................................... 18-1
18.2.2 Terminology .............................................................................................................. 18-1
18.2.3 Block Diagram .......................................................................................................... 18-2
18.3 External Signal Description .......................................................................................... 18-2
18.3.1 SDRAM Data Bus (SDDATA[31:0]) ....................................................................... 18-2
18.3.2 SDRAM Address Bus (SDADDR[12:0]) ................................................................. 18-2
18.3.3 SDRAM Bank Addresses (SDBA[1:0]) ................................................................... 18-2
18.3.4 SDRAM Row Address Strobe (RAS) ....................................................................... 18-3
18.3.5 SDRAM Column Address Strobe (CAS) ................................................................. 18-3
18.3.6 SDRAM Chip Selects (SDCS[3:0]) .......................................................................... 18-3
18.3.7 SDRAM Write Data Byte Mask (SDDM[3:0]) ........................................................ 18-3
18.3.8 SDRAM Data Strobe (SDDQS[3:0]) ........................................................................ 18-3
18.3.9 SDRAM Clock (SDCLK[1:0]) ................................................................................. 18-3
18.3.10 Inverted SDRAM Clock (SDCLK[1:0]) ................................................................... 18-3
18.3.11 SDRAM Write Enable (SDWE) ............................................................................... 18-3
18.3.12 SDRAM Clock Enable (SDCKE) ............................................................................. 18-4