Freescale Semiconductor MCF5480 - Manual (Page 16)

MCF548x Reference Manual, Rev. 3
xvi Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
11.1.1 Overview ................................................................................................................... 11-1
11.1.2 Modes of Operation .................................................................................................. 11-1
11.2 External Signals ............................................................................................................ 11-2
11.3 Memory Map/Register Definition ................................................................................ 11-2
11.3.1 GPT Enable and Mode Select Register (GMSn) ...................................................... 11-3
11.3.2 GPT Counter Input Register (GCIRn) ...................................................................... 11-5
11.3.3 GPT PWM Configuration Register (GPWMn) ........................................................ 11-6
11.3.4 GPT Status Register (GSRn) .................................................................................... 11-7
11.4 Functional Description .................................................................................................. 11-8
11.4.1 Timer Configuration Method .................................................................................... 11-8
11.4.2 Programming Notes .................................................................................................. 11-8
Chapter 12
Slice Timers (SLT)
12.1 Introduction ................................................................................................................... 12-1
12.1.1 Overview ................................................................................................................... 12-1
12.2 Memory Map/Register Definition ................................................................................ 12-1
12.2.1 SLT Terminal Count Register (STCNTn) ................................................................ 12-2
12.2.2 SLT Control Register (SCRn) ................................................................................... 12-2
12.2.3 SLT Timer Count Register (SCNTn) ........................................................................ 12-3
12.2.4 SLT Status Register (SSRn) ..................................................................................... 12-4
Chapter 13
Interrupt Controller
13.1 Introduction ................................................................................................................... 13-1
13.1.1 68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1
13.1.1.1 Interrupt Controller Theory of Operation ............................................................. 13-2
13.2 Memory Map/Register Descriptions ............................................................................. 13-4
13.2.1 Register Descriptions ................................................................................................ 13-5
13.2.1.1 Interrupt Pending Registers (IPRH, IPRL) ........................................................... 13-5
13.2.1.2 Interrupt Mask Register (IMRH, IMRL) .............................................................. 13-7
13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL) ............................................... 13-8
13.2.1.4 Interrupt Request Level Register (IRLR) ........................................................... 13-10
13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR) ...................... 13-10
13.2.1.6 Interrupt Control Registers 1–63 (ICRn) ............................................................ 13-11
13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ......... 13-13