Freescale Semiconductor MCF5480 - Manual (Page 21)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xxi
Contents
Paragraph
Number
Title
Page
Number
18.8.9 Perform Two Refresh Cycles .................................................................................. 18-31
18.8.10 Clear the Reset DLL Bit in the Mode Register ...................................................... 18-32
18.8.11 Enable Automatic Refresh and Lock Mode Register ............................................ 18-33
18.8.12 Initialization Code ................................................................................................... 18-34
Chapter 19
PCI Bus Controller
19.1 Introduction ................................................................................................................... 19-1
19.1.1 Block Diagram .......................................................................................................... 19-1
19.1.2 Overview ................................................................................................................... 19-1
19.1.3 Features ..................................................................................................................... 19-1
19.2 External Signal Description .......................................................................................... 19-2
19.2.1 Address/Data Bus (PCIAD[31:0]) ............................................................................ 19-2
19.2.2 Command/Byte Enables (PCICXBE[3:0]) ............................................................... 19-2
19.2.3 Device Select (PCIDEVSEL) ................................................................................... 19-3
19.2.4 Frame (PCIFRAME) ................................................................................................. 19-3
19.2.5 Initialization Device Select (PCIIDSEL) .................................................................. 19-3
19.2.6 Initiator Ready (PCIIRDY) ....................................................................................... 19-3
19.2.7 Parity (PCIPAR) ....................................................................................................... 19-3
19.2.8 PCI Clock (CLKIN) .................................................................................................. 19-3
19.2.9 Parity Error (PCIPERR) ............................................................................................ 19-3
19.2.10 Reset (PCIRESET) .................................................................................................. 19-3
19.2.11 System Error (PCISERR) ........................................................................................ 19-3
19.2.12 Stop (PCISTOP) ...................................................................................................... 19-3
19.2.13 Target Ready (PCITRDY) ....................................................................................... 19-4
19.3 Memory Map/Register Definition ................................................................................ 19-4
19.3.1 PCI Type 0 Configuration Registers ......................................................................... 19-6
19.3.1.1 Device ID/Vendor ID Register (PCIIDR)—PCI Dword Addr 0 .......................... 19-7
19.3.1.2 PCI Status/Command Register (PCISCR)—PCI Dword Addr 1 ......................... 19-7
19.3.1.3 Revision ID/Class Code Register (PCICCRIR)—PCI Dword 3 .......................... 19-9
19.3.1.4 Configuration 1 Register (PCICR1)—PCI Dword 3 .......................................... 19-10
19.3.1.5 Base Address Register 0 (PCIBAR0)—PCI Dword 4 ........................................ 19-11
19.3.1.6 Base Address Register 1 (PCIBAR1)—PCI Dword 5 ........................................ 19-12
19.3.1.7 CardBus CIS Pointer Register PCICCPR—PCI Dword A ................................ 19-12
19.3.1.8 Subsystem ID/Subsystem Vendor ID Registers PCISID—PCI Dword B .......... 19-12
19.3.1.9 Expansion ROM Base Address PCIERBAR—PCI Dword C ............................ 19-13
19.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D ................................... 19-13
19.3.1.11 Configuration 2 Register (PCICR2)—PCI Dword F .......................................... 19-13
19.3.2 General Control/Status Registers ............................................................................ 19-13
19.3.2.1 Global Status/Control Register (PCIGSCR) ....................................................... 19-14