Freescale Semiconductor MCF5480 - Manual (Page 23)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xxiii
Contents
Paragraph
Number
Title
Page
Number
19.4.6.6 PCI Commands ................................................................................................... 19-69
19.4.6.7 FIFO Considerations ........................................................................................... 19-69
19.4.6.8 Alarms ................................................................................................................. 19-69
19.4.6.9 Bus Errors ........................................................................................................... 19-70
19.4.7 PCI Clock Scheme .................................................................................................. 19-70
19.4.8 Interrupts ................................................................................................................. 19-70
19.4.8.1 PCI Bus Interrupts .............................................................................................. 19-70
19.4.8.2 Internal Interrupt ................................................................................................. 19-70
19.5 Application Information ............................................................................................. 19-70
19.5.1 XL Bus-Initiated Transaction Mapping .................................................................. 19-70
19.5.2 Address Maps ......................................................................................................... 19-71
19.5.2.1 Address Translation ............................................................................................ 19-72
19.6 XL Bus Arbitration Priority ........................................................................................ 19-75
Chapter 20
PCI Bus Arbiter Module
20.1 Introduction ................................................................................................................... 20-1
20.1.1 Block Diagram .......................................................................................................... 20-1
20.1.2 Overview ................................................................................................................... 20-1
20.1.3 Features ..................................................................................................................... 20-2
20.2 External Signal Description .......................................................................................... 20-2
20.2.1 Frame (PCIFRM) ...................................................................................................... 20-2
20.2.2 Initiator Ready (PCIIRDY) ....................................................................................... 20-2
20.2.3 PCI Clock (CLKIN) .................................................................................................. 20-2
20.2.4 External Bus Grant (PCIBG[4:1]) ............................................................................ 20-2
20.2.5 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) ................................ 20-3
20.2.6 External Bus Request (PCIBR[4:1]) ......................................................................... 20-3
20.2.7 External Request/Grant Input (PCIBR0/PCIGNTIN) .............................................. 20-3
20.3 Register Definition ........................................................................................................ 20-3
20.3.1 PCI Arbiter Control Register (PACR) ...................................................................... 20-3
20.3.2 PCI Arbiter Status Register (PASR) ......................................................................... 20-5
20.4 Functional Description .................................................................................................. 20-5
20.4.1 External PCI Requests .............................................................................................. 20-5
20.4.2 Arbitration ................................................................................................................. 20-6
20.4.2.1 Hidden Bus Arbitration ......................................................................................... 20-6
20.4.2.2 Arbitration Scheme ............................................................................................... 20-6
20.4.2.3 Arbitration Latency ............................................................................................... 20-7
20.4.2.4 Arbitration Examples ............................................................................................ 20-7
20.4.3 Master Time-Out ....................................................................................................... 20-9
20.5 Reset ............................................................................................................................ 20-10