Freescale Semiconductor MCF5480 - Manual (Page 793)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 26-31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 WFR TIMER FRMEN GR IP_
MSK
FAE_
MSK
RXW
_MSK
UF_
MSK
OF_
MSK
TXW_
MSK
0 0
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTR
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x8668 (PSCRFCR0); 0x8768 (PSCRFCR1); 0x8868 (PSCRFCR2) ; 0x8968 (PSCRFCR3)
and MBAR + 0x8688 (PSCTFCR0); 0x8788 (PSCTFCR1); 0x8888 (PSCTFCR2); 0x8988 (PSCTFCR3)
Figure 26-21. Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn)
Table 26-31. PSCRFCRn and PSCRTFCRn Field Descriptions
Bits Name Description
31–30 — Reserved, should be cleared.
29 WFR Write frame. When this bit is set, the FIFO controller assumes the next write to its data port is the
end of a frame, and will tag the incoming data accordingly. This bit is automatically cleared by a write
to the data port.
This bit is only implemented in the PSCTFCRn.
28 TIMER Timer mode enable. When this bit is set, the FIFO controller will suppress a frame ready request for
service from occuring until the timer expires. The timer period can be programmed using the
COUNTER[15:0] bits. A request for service will be made every (COUNTER[15:0] * 64) cycles as
long as a valid frame exists in the FIFO. Alarm requests are not affected by this mode. Further, the
timer is restarted anytime a read or a write to the FIFO Data register occurs. This indicates that
either the FIFO currently has the DMA’s attention or that data is still being transfered and that there
is the possibility that a naturally generated alarm will occur. This bit is only meaningful when Frame
Mode is enabled via the FRMEN bit.
27 FRMEN Frame mode enable
0 Frame mode disabled.
1 Frame mode enabled.
26–24 GR Granularity
For Transmitter: These bits control the high “watermark” point at which the FIFO will negate its
alarm condition (i.e. request for data). It represents the number of Free Bytes multiplied by 4. For
example, if GR = 000, the FIFO will wait to become completely full before it stops requesting data.
If GR = 001, the FIFO will stop requesting data when it has only one longword of space remaining.
For Receiver: These bits control the high “watermark” point at which the FIFO will negate its alarm
condition (i.e. its request to empty its data). It represents the number of Data Bytes multiplied by 4.
For example, if GR = 001, the FIFO will stop requesting service when it has only one longword of
data remaining
23 IP_MSK Illegal pointer mask. When this bit is set, the FIFO controller masks the status register’s IP bit from
generating an error.
22 FAE_MSK Frame accept error mask. When this bit is set, the FIFO controller masks the status register’s FAE
bit from generating an error.