Freescale Semiconductor MCF5480 - Manual (Page 47)

Terminology and Notational Conventions
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xlvii
Terminology and Notational Conventions
Table iii shows notational conventions used throughout this document.
UART Universal asynchronous/synchronous receiver transmitter
XLB bus Internal 64-bit bus
Table iii. Notational Conventions
Instruction Operand Syntax
Opcode Wildcard
cc Logical condition (example: NE for not equal)
Register Specifications
An Any address register n (example: A3 is address register 3)
Ay,Ax Source and destination address registers, respectively
Dn Any data register n (example: D5 is data register 5)
Dy,Dx Source and destination data registers, respectively
Rc Any control register (example VBR is the vector base register)
Rm MAC registers (ACC, MAC, MASK)
Rn Any address or data register
Rw Destination register w (used for MAC instructions only)
Ry,Rx Any source and destination registers, respectively
Xi index register i (can be an address or data register: Ai, Di)
Register Names
ACC MAC accumulator register
CCR Condition code register (lower byte of SR)
MACSR MAC status register
MASK MAC mask register
PC Program counter
SR Status register
Port Name
PSTDDATA Processor status/debug data port
Miscellaneous Operands
#<data> Immediate data following the 16-bit operation word of the instruction
<ea> Effective address
Table ii. . Acronyms and Abbreviated Terms (continued)
Term Meaning