Freescale Semiconductor MCF5480 User Manual
Page 492
MCF548x Reference Manual, Rev. 3
19-8
Freescale Semiconductor
Table 19-4. PCISCR Field Descriptions
Bits
Name
Description
31
PE
Parity error detected. This bit is set when a parity error is detected, even if the PCISCR[PER] is cleared.
This bit is cleared by a PCI configuration cycle writing a ‘1’ to the bit. Writing ‘0’ has no effect.
30
SE
System error signalled. This bit is set whenever the PCI controller generates a PCI system error on the
PCISERR line. This bit is cleared by a PCI configuration cycle writing a ‘1’ to the bit. Writing ‘0’ has no
effect.
29
MA
Master abort received. This bit is set whenever the PCI controller is the PCI master and terminates a
transaction (except for a special cycle) with a master-abort. This bit is cleared by a PCI configuration
cycle writing a ‘1’ to the bit. Writing ‘0’ has no effect.
28
TR
Target abort received. This bit is set whenever the PCI controller is the PCI master and a transaction
is terminated by a target-abort from the currently addressed target. This bit is cleared by a PCI
configuration cycle writing a ‘1’ to the bit. Writing ‘0’ has no effect.
27
TS
Target abort signalled. This bit is set whenever the PCI controller is the target and it terminates a
transaction with a target-abort. This bit is cleared by a PCI configuration cycle writing a ‘1’ to the bit.
Writing ‘0’ has no effect.
26–25
DT
DEVSEL timing. Fixed to ‘01’. These bits encode a medium DEVSEL timing. This defines the slowest
DEVSEL timing as meduim timing when the PCI controller is the target (except configuration
accesses).
24
DP
Master data parity error. This bit applies only when the PCI controller is the master and is set only if the
following conditions are met:
• The PCI controller-as-master sets PERR itself during a read or the PCI controller-as-master
detected it asserted by the target during a write
• The PCISCR[PER] bit is set
This bit is cleared by a PCI configuration cycle writing a ‘1’ to the bit. Writing ‘0’ has no effect.
23
FC
Fast back-to-back capable. Fixed to 1. This read-only bit indicates that the PCI controller as target is
capable of accepting fast back-to-back transactions with other targets.
22
R
Reserved. Fixed to 0. Prior to the 2.2 PCI Spec, this was the UDF (user defined features) supported bit.
0 Does not support UDF
1 Supported user defined features
21
66M
66 MHz capable. Fixed to 1. This bit indicates that the PCI controller is 66 MHz capable.
20
C
Capabilities list. Fixed to 0. This bit indicates that the PCI controller does not implement the New
Capabilities List Pointer Configuration Register in DWORD 13 of the configuration space.
19–10
—
Reserved, should be cleared.
9
F
Fast back-to-back transfer enable. This bit controls whether or not the PCI controller as master can do
fast back-to-back transactions to different devices. Initialization software should set this bit if all targets
are fast back-to-back capable.
0 Fast back-to-back transactions are only allowed to the same device
1 The master is allowed to generate fast back-to-back transactions to different devices.
8
S
SERR enable. This bit is an enable bit for the
PCISERR driver.
0 PCISERR driver disabled
1 PCISERR driver enabled
Note: Address parity errors are reported only if this bit and bit 6 are set.
7
ST
Address and data stepping. Fixed to 0. This bit indicates that the PCI controller never uses
address/data stepping. Initialization software should write a 0 to this bit location.