Freescale Semiconductor MCF5480 - Manual (Page 632)

MCF548x Reference Manual, Rev. 3
22-30 Freescale Semiconductor
Figure 22-22. AFEU Status Register (AFSR)
Table 22-19 describes AFEU status register fields.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 HALT IFW OFR IE ID RD 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x28028
Table 22-19. AFSR Field Descriptions
Bits Name Description
31–30 — Reserved, should be cleared.
29 HALT Halt. Indicates that the AFEU has halted due to an error.
0 AFEU not halted
1 AFEU halted
Note: Because the error causing the AFEU to stop operating may be masked in the interrupt status
register, the status register is used to provide a second source of information regarding errors
preventing normal operation.
28 IFW Input FIFO writable. The controller uses this signal to determine if the AFEU can accept the next
BURST SIZE block of data.
0 AFEU Input FIFO not ready
1 AFEU Input FIFO ready
Note: The SEC implements flow control to allow larger than FIFO sized blocks of data to be
processed with a single key/IV. The AFEU signals to the crypto-channel that a ‘burst size’ amount
of space is available in the FIFO.
27 OFR Output FIFO readable. The controller uses this signal to determine if the AFEU can source the next
burst size block of data.
0 AFEU Output FIFO not ready
1 AFEU Output FIFO ready
Note: The SEC implements flow control to allow larger than FIFO sized blocks of data to be
processed with a single key/IV. The AFEU signals to the crypto-channel that a “Burst Size” amount
of data is available in the FIFO.
26 IE Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the
controller interrupt status register (
Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and
SISRL) ”).
0 AFEU is not signaling error
1 AFEU is signaling error