Freescale Semiconductor MCF5480 - Manual (Page 187)

MMU Implementation
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 5-21
When MMUAR is used for a TLB address, bits FA[5–0] also have this address format for CF4e. The
remaining form address bits (FA[31–6]) are ignored when this register is being used for a TLB address.
5.6.2 TLB Replacement Algorithm
The instruction and data TLBs provide low-latency access to recently used instruction and operand
translation information. CF4e ITLBs and DTLBs are 32-entry fully associative caches. The 32 ITLB
entries are searched on each instruction reference; the 32 DTLB entries are searched on each operand
reference.
CF4e TLBs are software controlled. The TLB clear-all function clears valid bits on every TLB entry and
resets the replacement logic. A new valid entry is loaded in the TLBs may be designated as locked and
unavailable for allocation. TLB hits to locked entries do not update replacement algorithm information.
When a new TLB entry needs to be allocated, the user can specify the exact TLB entry to be updated
(through MMUOR[ADR] and MMUAR) or let TLB hardware pick the entry to update based on the
replacement algorithm. A pseudo-least-recently used (PLRU) algorithm picks the entry to be replaced on
a TLB miss. The algorithm works as follows:
• If any element is empty (non-valid), use the lowest empty element as the allocate entry (that is,
entry 0 before 1, 2, 3, and so on).
• If all entries are valid, use the entry indicated by the PLRU as the allocate entry.
The PLRU algorithm uses 31 most-recently used state bits per TLB to track the TLB hit history. Table 5-13
lists these state bits.
Table 5-13. PLRU State Bits
State Bits Meaning
rdRecent31To16 A one indicates 31To16 is more recent than 15To00
rdRecent31To24 A one indicates 31To24 is more recent than 23To16
rdRecent15To08 A one indicates 15To08 is more recent than 07To00
rdRecent31To28 A one indicates 31To28 is more recent than 27To24
rdRecent23To20 A one indicates 23To20 is more recent than 19To16
rdRecent15To12 A one indicates 15To12 is more recent than 11To08
rdRecent07To04 A one indicates 07To04 is more recent than 03To00
rdRecent31To30 A one indicates 31To30 is more recent than 29To28
rdRecent27To26 A one indicates 27To26 is more recent than 25To24
rdRecent23To22 A one indicates 23To22 is more recent than 21To20
rdRecent19To18 A one indicates 19To18 is more recent than 17To16
rdRecent15To14 A one indicates 15To14 is more recent than 13To12
rdRecent11To10 A one indicates 11To10 is more recent than 09To08
rdRecent07To06 A one indicates 07To06 is more recent than 05To04
rdRecent03To02 A one indicates 03To02 is more recent than 01To00
rdRecent31 A one indicates 31 is more recent than 30
rdRecent29 A one indicates 29 is more recent than 28