Freescale Semiconductor MCF5480 - Manual (Page 761)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 25-9
At the rising edge of the clock in cycle 8, the cAcknowledge signal is asserted. At that point the percent
counter begins to count. At the rising edge of clock 10, cAcknowledge is deasserted and the counter reaches
the high time value. As a result of the counter reaching the high time value (2), cInitiator is deasserted.
The counter does not stop counting; however, it continues to count toward the period reference value (8).
At the rising edge of clock 16, the timer has timed out, it is reset to its initial value (1), and the cInitiator
signal is asserted.
The next two periods act in a similar fashion. What is most important to be aware of in this diagram is the
fact that, unlike the fixed timer channel, the variable timer does not have a fixed period. The percent
counter only begins counting when cAcknowledge has arrived. It counts to the period value then resets and
waits again.
The first period is from clock 1 to clock 16 or 15 clock cycles. The second period is only 8 cycles long and
is from clock 16 to clock 24. The third cycle is 10 cycles long running from clock 24 to 34.
The final period is somewhat undefined as the cAcknowledge signal has not been asserted yet. Therefore,
it is at least 13 cycles long and can be any value greater than that.
Figure 25-7. Variable Timer Channel in Initiator Mode
Percent
Counter Value
cAcknowledge
2 3 4 5 6 7 8 1 2 3 4 5 6
CLK
7 8 2 3 4 5 6 7 8
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
cInitiator
1
000001 000001 000001