Freescale Semiconductor MCF5480 - Manual (Page 375)

External Pin Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 15-3
• External DMA request and acknowledge (DMA)
• PCI bus access (PCIGNT, PCIREQ)
• Ethernet data and control (FEC0H, FEC0L, FEC1H, FEC1L, FECI2C)
• I
2
C serial control (FECI2C)
• DMA serial peripheral interface (DSPI)
• Programmable serial control (PSC1PSC0 and PSC3PSC2)
15.1.2 Features
The MCF548x GPIO module includes these distinctive features:
• Control of primary function use of the supported GPIO ports indicated in Section 15.1.1,
“Overview”
• General purpose I/O support for all ports:
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
15.2 External Pin Description
The MCF548x GPIO module controls the functionality of several external pins. These pins are listed in
Table 15-1 .
Table 15-1. MCF548x GPIO Module External Pins
Primary
Function
(Pin Name)
1
GPIO
Alternate
Function 1
Alternate
Function 2
Description
Flexbus Control
BWE[3:2] PFBCTL[7:6] BE / BWE[3:2] TSIZ[1:0] Byte write strobes for external data transfer / Port
FBCTL[7:4] / Byte enables for external data transfer /
FlexBus transfer size
BWE[1:0] PFBCTL[5:4] BE / BWE[1:0] FBADDR[1:0] Byte write strobes for external data transfer / Port
FBCTL[7:4] / Byte enables for external data transfer /
FlexBus address[1:0]
OE PFBCTL3 — — Output enable for external reads / Port FBCTL3
R/W PFBCTL2 TBST — Read/write indication for external data transfer / Port
FBCTL2 / FlexBus transfer burst
TA PFBCTL1 — — Transfer acknowledge for external data transfer / Port
FBCTL1
ALE PFBCTL0 TBST — Address latch enable indication for external data transfer
/ Port FBCTL0 / FlexBus transfer burst
Flexbus Chip Selects
FBCS[5:1] PFBCS[5:1] — — Flexbus chip selects 5 – 1 / Port FBCS[5:4]
DMA Controller
DACK1 PDMA3 TOUT1 — DMA acknowledge 1 / Port DMA3 / GP timer output 1