Freescale Semiconductor MCF5480 - Manual (Page 427)

Chip-Select Operation
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 17-11
19–18 RDAH Read Address Hold or (Deselect). This field controls the address and attribute hold time after the
termination during a read cycle that hits in the chip-select address space. The hold time only applies
at the end of a transfer. Therefore, a burst transfer only has a hold time added after the last bus
cycle.
RDAH = 00; Hold address and attributes one cycle after FBCSn
negates on reads. (Default FBCSn)
01 Hold address and attributes two cycles after FBCSn negates on reads.
10 Hold address and attributes three cycles after FBCSn negates on reads.
11 Hold address and attributes four cycles after FBCSn negates on reads. (Reset FBCS0)
17–16 WRAH Write Address Hold or (Deselect). This field controls the address, data and attribute hold time after
the termination of a write cycle that hits in the chip-select address space.The hold time only applies
at the end of a transfer. Therefore, a burst transfer only has a hold time added after the last bus
cycle.
WRAH = 00; Hold address and attributes one cycle after FBCSn
negates on writes. (Default
FBCSn)
01 Hold address and attributes two cycles after FBCSn
negates on writes.
10 Hold address and attributes three cycles after FBCSn negates on writes.
11 Hold address and attributes four cycles after FBCSn negates on writes. (Reset FBCS0)
15–10 WS Wait states. The number of wait states inserted after FBCSn asserts and before an internal transfer
acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). If
AA = 0, TA must be asserted by the external system regardless of the number of wait states
generated. In that case, the external transfer acknowledge ends the cycle. An external TA
supersedes the generation of an internal TA.
9 — Reserved, should be cleared.
8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for
accesses specified by the chip-select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding FBCSn and
the external system asserts an external TA before the wait-state countdown asserts the internal TA,
the cycle is terminated. Burst cycles increment the address bus between each internal termination.
7–6 PS Port size. Specifies the width of the data port associated with each chip-select. It determines where
data is driven during write cycles and where data is sampled during read cycles.
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5 BEM Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that
must be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide
the appropriate mode of byte enable support in support of these SRAMs.
0 Neither BE or BWE is asserted for reads. BWE is generated for data write only.
1 BE is asserted for reads; BWE is asserted for writes.
4 BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each
FBCSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8-
and 16-bit ports and word reads from 8-bit ports.
Table 17-9. CSCRn Field Descriptions (Continued)
Bits Name Description