2 ad5-flexbus size configuration (fbsize), 3 ad4-32-bit flexbus configuration (fbmode), 4 ad3-byte enable configuration (beconfig) – Freescale Semiconductor MCF5480 User Manual
Page 93: Ad5—flexbus size configuration (fbsize) -23, Ad4—32-bit flexbus configuration (fbmode) -23, Ad3—byte enable configuration (beconfig) -23, 2 ad5—flexbus size configuration (fbsize), 3 ad4—32-bit flexbus configuration (fbmode), 4 ad3—byte enable configuration (beconfig)
MCF548x External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
2-23
Figure 2-2. CLKIN, Internal Bus, and Core Clock Ratios
2.2.6.2
AD5—FlexBus Size Configuration (FBSIZE)
At reset, the enabling and disabling of BE/BWE[3:0] versus TSIZ[1:0] and ADDR[1:0] is determined by
the logic level driven on AD5 at the rising edge of RSTI. FBSIZE is multiplexed with AD5 and sampled
only at reset.
shows how the AD5 logic level corresponds to the BE/BWE[3:0] function.
2.2.6.3
AD4—32-bit FlexBus Configuration (FBMODE)
During reset, the FlexBus can be configured to operate in a non-multiplexed 32-bit address with 32-bit data
mode. In this mode, the 32-bit FlexBus AD[31:0] is used for the data bus, and the PCI bus PCIAD[31:0]
is used as the address bus. The FlexBus operating mode is determined by the logic level driven on AD4 at
the rising edge of RSTI.
shows how the logic level of AD4 corresponds to the FlexBus mode.
2.2.6.4
AD3—Byte Enable Configuration (BECONFIG)
The default byte enable mode of the boot FBCS0 is determined by the logic level driven on AD3 at the
rising edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM].
the logic level of AD3 corresponds to the byte enable mode for FBCS0 at reset.
Table 2-5. AD5/FBSIZE Selection of BE/BWE[3:0] Signals
AD5
FlexBus Byte Enable Mode
0
BE/BWE[3:0] used as byte/byte write
enables.
1
BE/BWE[3:2] configured as TSIZ[1:0].
BE/BWE[1:0] configured as FBADDR[1:0].
Table 2-6. AD4/FBMODE Selection of Non-Multiplexed
32-bit Address/32-bit Data Mode
AD4
FlexBus Operating Mode
0
AD[31:0] used for data.
PCIAD[31:0] used for address
1
1
If the non-multiplexed 32-bit address/32-bit data mode is selected, the PCI bus
cannot be used.
1
PCIAD[31:0] used for PCI bus.
AD[31:0] used for both address and data.
25 40 50 60 70
70 80 90 100 110 120 130 140 150 160 170 180 190 200
60
25.0
50.0
100.0
CLKIN (MHz)
Core Clock (MHz)
Core Clock
CLKIN
200.0
40 50 60 70 80 90 100
30
50.0
100.0
Internal Clock
Internal Clock (MHz)
2x
2x
25.0
200.0
2x
4x
100.0