Freescale Semiconductor MCF5480 - Manual (Page 791)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 26-29
Table 26-30. PSCRFSRn and PSCTFSRn Field Descriptions
Bits Name Description
15 IP Illegal pointer. This bit signifies an illegal pointer condition in the FIFO controller. A 1 in this bit will
cause a FIFO error condition in the PSCISR. This bit will remain set until a 1 is written to this bit
location.
0 No illegal pointer condition.
1 An address outside the FIFO controller’s memory range has been written to one of the
user-visible pointers.
14 TXW Transmit wait condition. This bit indicates that the bus is incurring wait states because there is not
enough data in the FIFO to remove data without causing underflow. A 1 in this bit will cause a FIFO
error condition in the PSCISR. This bit will remain set until a 1 is written to this bit location. Valid only
for TxFIFO.
0 No Error
1 When the FIFO is empty and the CODEC requested to read. Writing a 1 clears this bit.
13-12 TAG Holds the last read tag information.
11-8 FRM Frame indicator. This bus provides a frame status indicator for non-DMA applications.
1000 A frame boundary has occurred on the [31:24] byte of the data bus
0100 A frame boundary has occurred on the [23:16] byte of the data bus
0010 A frame boundary has occurred on the [15:8] byte of the data bus
0001 A frame boundary has occurred on the [7:0] byte of the data bus
7 FAE Frame accept error. This bit indicates a frame accept error in the FIFO controller and will assert in
two scenarios. 1) The user has over-written data in a transmit FIFO for a frame that needs to be
retried. 2) The user has read data from a receive FIFO for a frame that has subsequently been
rejected. A 1 in this bit will cause a FIFO error condition in the PSCISR. This bit will remain set until
a 1 is written to this bit location. This bit is inactive when the FIFO is not programmed for frame mode.
0 No frame accept error.
1 Frame accept error.
6 RXW Receive wait condition. This bit indicates that the bus is incurring wait states because there is not
enough room in the FIFO to accept the data without causing overflow. A 1 in this bit will cause a FIFO
error condition in the PSCISR. This bit will remain set until a 1 is written to this bit location. Valid only
for RxFIFO.
0 No error.
1 When the FIFO is full and the CODEC received more data. Writing a 1 clears this bit.
5 UF FIFO underflow. This bit signifies that the read pointer has surpassed the write pointer. A 1 in this
bit will cause a FIFO error condition in the PSCISR. This bit will remain set until a 1 is written to this
bit location.
0 No Underflow.
1 Read pointer has passed the write pointer. Writing a 1 to this bit clears the UF indicator. Writing
zero has no effect.
4 OF FIFO Overflow. This bit signifies that the write pointer has surpassed the read pointer. A 1 in this bit
will cause a FIFO error condition in the PSCISR. This bit will remain set until a 1 is written to this bit
location.
0 No overflow.
1 Write pointer has passed the read pointer. Writing a 1 to this bit clears the OF indicator. Writing
a zero has no effect.
3 FRMRDY Frame ready. This read only bit indicates that there is framed data ready. All complete frames must
be read from the FIFO to clear this alarm. This alarm will only be set while in frame mode.
0 No complete frames exist in the FIFO.
1 One or more complete frames exist in the FIFO.