Freescale Semiconductor MCF5480 User Manual
Page 538
MCF548x Reference Manual, Rev. 3
19-54
Freescale Semiconductor
tells the community of devices on the PCI bus that the bridge that “owns” the PCI bus has already
performed the bus number comparison and verified that the request targets a device on its bus.
shows the contents of the AD bus during the address phase of the Type 0 configuration
access.
Figure 19-49. Type 0 Configuration Transaction:
Contents of the AD Bus During Address Phase
Address bits [10:8] identify the target function and bits AD[7:2] select one of the 64 configuration Dwords
within the target function’s configuration space. For Type 0 configuration transactions, the target device’s
IDSEL pin must be asserted. The upper 21 address lines are commonly used as IDSELs since they are not
used during the address phase of a type 0 configuration transaction.
For a Type 1 access where the target bus is a bus that is subordinate to the local PCI bus (bus 0), the
configuration transaction is still initiated on bus 0, but the bit pattern AD[1:0] indicates that none of the
devices on this bus are the target of the transaction. Rather, only PCI-to-PCI bridges residing on the local
bus should pay attention to the transaction because it targets a device on a bus further out in the hierarchy
beyond a PCI-to-PCI bridge that is attached to the local PCI bus (bus 0). This is accomplished by initiating
a Type 1 configuration transaction (setting AD[1:0] to 0b01 during the address phase). This pattern
instructs all functions other than PCI-to-PCI bridges that the transaction is not for any of them.
illustrates the contents of the AD bus during the address phase of the Type 1 configuration
access.
Figure 19-50. Type 1 Configuration Transaction:
Contents of the AD Bus During Address Phase
During the address phase of a Type 1 configuration access, the information on the AD bus is formatted as
follows:
•
PCIAD[1:0] contains 0b01, identifying this as a Type 1 configuration access.
•
PCIAD[7:2] identifies one of 64 configuration Dwords within the target devices’s configuration
space.
•
PCIAD[10:8] identifies one of the eight functions within the target physical device.
•
PCIAD[15:11] identifies one of 32 physical devices. This field is used by the bridge to select which
device’s IDSEL line to assert.
•
PCIAD[23:16] identifies one of 256 PCI buses in the system.
•
PCIAD[31:24] are reserved and are cleared to zero.
During a Type 1 configuration access, PCI devices ignore the state of their IDSEL inputs; PCI devices only
respond to Type 0 accesses. When any PCI-to-PCI bridge latches a Type 1 configuration access (command
= configuration read or write and AD[1:0] = 0b01) on its primary side, it must determine whether the bus
number field on the AD bus matches the number of its secondary bus or if the field is within the range of
its subordinate buses. If the bus number matches, it should claim and pass the configuration access onto
31
11 10
8
7
2
1
0
Reserved
Function Number
Dword Number
0
0
Target Configuration Doubleword Number
31
24 23
16 15
11 10
8
7
2
1
0
Reserved
Bus Number
Device Number
Function Number
Dword Number
0
1
Doubleword Number in the Device’s Configuration Space