Freescale Semiconductor MCF5480 - Manual (Page 33)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xxxiii
Contents
Paragraph
Number
Title
Page
Number
26.7.2.5 SIR Mode ............................................................................................................ 26-52
26.7.2.6 MIR Mode .......................................................................................................... 26-53
26.7.2.7 FIR Mode ............................................................................................................ 26-54
26.7.3 Programming .......................................................................................................... 26-55
26.7.3.1 MIR Mode .......................................................................................................... 26-55
26.7.3.2 FIR Mode ............................................................................................................ 26-56
Chapter 27
DMA Serial Peripheral Interface (DSPI)
27.1 Overview ....................................................................................................................... 27-1
27.2 Features ......................................................................................................................... 27-1
27.3 Block Diagram .............................................................................................................. 27-2
27.4 Modes of Operation ...................................................................................................... 27-2
27.4.1 Master Mode ............................................................................................................. 27-2
27.4.2 Slave Mode ............................................................................................................... 27-2
27.5 Signal Description ......................................................................................................... 27-3
27.5.1 Overview ................................................................................................................... 27-3
27.5.2 Detailed Signal Descriptions .................................................................................... 27-3
27.5.2.1 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS) ................................... 27-3
27.5.2.2 DSPI Peripheral Chip Selects 2–3 (DSPICS[2:3]) ............................................... 27-3
27.5.2.3 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe (DSPICS5/PCSS) 27-3
27.5.2.4 DSPI Serial Input (DSPISIN) ............................................................................... 27-4
27.5.2.5 DSPI Serial Output (DSPISOUT) ........................................................................ 27-4
27.5.2.6 DSPI Serial Clock (DSPISCK) ............................................................................. 27-4
27.6 Memory Map and Registers .......................................................................................... 27-4
27.6.1 DSPI Module Configuration Register (DMCR) ....................................................... 27-5
27.6.2 DSPI Transfer Count Register (DTCR) .................................................................... 27-7
27.6.3 DSPI Clock and Transfer Attributes Registers 0–7 (DCTARn) ............................... 27-7
27.6.4 DSPI Status Register (DSR) ................................................................................... 27-11
27.6.5 DSPI DMA/Interrupt Request Select Register (DIRSR) ........................................ 27-13
27.6.6 DSPI Tx FIFO Register (DTFR) ............................................................................ 27-15
27.6.7 DSPI Rx FIFO Register (DRFR) ............................................................................ 27-16
27.6.8 DSPI Tx FIFO Debug Registers 0–3 (DTFDRn) ................................................... 27-17
27.6.9 DSPI Rx FIFO Debug Registers 0–3 (DRFDRn) ................................................... 27-17
27.7 Functional Description ................................................................................................ 27-18
27.7.1 Start and Stop of DSPI Transfers ............................................................................ 27-19
27.7.2 Serial Peripheral Interface (SPI) ............................................................................ 27-20
27.7.2.1 Master Mode ....................................................................................................... 27-20
27.7.2.2 Slave Mode ......................................................................................................... 27-20
27.7.2.3 FIFO Disable Operation ..................................................................................... 27-21