Freescale Semiconductor MCF5480 - Manual (Page 9)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor ix
Contents
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Title
Page
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Chapter 3
ColdFire Core
3.1 Core Overview ................................................................................................................ 3-1
3.2 Features ........................................................................................................................... 3-1
3.2.1 Enhanced Pipelines ..................................................................................................... 3-2
3.2.1.1 Instruction Fetch Pipeline (IFP) .............................................................................. 3-3
3.2.1.2 Operand Execution Pipeline (OEP) ........................................................................ 3-4
3.2.1.3 Harvard Memory Architecture ............................................................................... 3-6
3.2.2 Debug Module Enhancements .................................................................................... 3-6
3.3 Programming Model ....................................................................................................... 3-7
3.3.1 User Programming Model .......................................................................................... 3-9
3.3.1.1 Data Registers (D0–D7) ......................................................................................... 3-9
3.3.1.2 Address Registers (A0–A6) .................................................................................... 3-9
3.3.2 User Stack Pointer (A7) ............................................................................................. 3-9
3.3.2.1 Program Counter (PC) ............................................................................................ 3-9
3.3.2.2 Condition Code Register (CCR) ............................................................................. 3-9
3.3.3 EMAC Programming Model .................................................................................... 3-10
3.3.4 FPU Programming Model ......................................................................................... 3-10
3.3.5 Supervisor Programming Model ............................................................................... 3-11
3.3.5.1 Status Register (SR) .............................................................................................. 3-12
3.3.5.2 Vector Base Register (VBR) ................................................................................ 3-12
3.3.5.3 Cache Control Register (CACR) .......................................................................... 3-13
3.3.5.4 Access Control Registers (ACR0–ACR3) ............................................................ 3-13
3.3.5.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ............................ 3-13
3.3.5.6 Module Base Address Register (MBAR) ............................................................. 3-13
3.3.6 Programming Model Table ....................................................................................... 3-13
3.4 Data Format Summary .................................................................................................. 3-15
3.4.1 Data Organization in Registers ................................................................................. 3-15
3.4.1.1 Integer Data Format Organization in Registers .................................................... 3-15
3.4.1.2 Integer Data Format Organization in Memory ..................................................... 3-16
3.4.2 EMAC Data Representation ..................................................................................... 3-17
3.4.2.1 Floating-Point Data Formats and Types ............................................................... 3-17
3.5 Addressing Mode Summary ......................................................................................... 3-18
3.6 Instruction Set Summary .............................................................................................. 3-19
3.6.1 Additions to the Instruction Set Architecture ........................................................... 3-19
3.6.2 Instruction Set Summary .......................................................................................... 3-22
3.7 Instruction Execution Timing ....................................................................................... 3-27
3.7.1 MOVE Instruction Execution Timing ...................................................................... 3-28
3.7.2 One-Operand Instruction Execution Timing ............................................................ 3-30
3.7.3 Two-Operand Instruction Execution Timing ............................................................ 3-31