Freescale Semiconductor MCF5480 - Manual (Page 105)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-1
Chapter 3
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF548x. The CF4e implementation
of the Version 4 (V4) core includes the floating-point unit (FPU), enhanced multiply-accumulate unit
(EMAC), and memory management unit (MMU); all are defined as optional in the V4 architecture. This
chapter also includes a full description of exception handling, data formats, an instruction set summary,
and a table of instruction timings.
3.1 Core Overview
The MCF548x is the first standard product to contain a Version 4e ColdFire microprocessor core. To create
this next-generation, high-performance core, many advanced microarchitectural techniques were
implemented. Most notable are a Harvard memory architecture, branch cache acceleration logic, and
limited superscalar dual-instruction issue capabilities, which together provide 308 (Dhrystone 2.1) MIPS
performance at 200 MHz.
The MCF548x core design emphasizes performance and backward compatibility, and represents the next
step on the ColdFire performance roadmap.
3.2 Features
The CF4e includes the following features defined as optional in the V4 core architecture:
• Floating-point unit (FPU)
• Virtual memory management unit (MMU)
• Enhanced multiply-accumulate unit (EMAC) for increased signal processing functionality plus
backward code compatibility with the MAC unit of previous ColdFire processors
V4 architecture features are defined as follows:
• Variable-length RISC, clock-multiplied core
• Revision B of the ColdFire instruction set architecture (ISA_B), providing new instructions to
improve performance and code density
• Two independent, decoupled pipelines—four-stage instruction fetch pipeline (IFP) and five-stage
operand execution pipeline (OEP) for increased performance
• Ten-instruction, FIFO buffer that decouples the IFP and OEP
• Limited superscalar design approaches dual-issue performance with the cost of a scalar execution
pipeline
• Two-level branch acceleration mechanism with a branch cache, plus a prediction table for
increased performance of conditional Bcc instructions
• 32-bit address bus supporting 4 Gbytes of linear address space
• 32-bit data bus
• 16 user-accessible, 32-bit-wide, general-purpose registers
• Supervisor/user modes for system protection
• Two separate stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack
pointer (USP)—that provide the required isolation between operating modes to support the MMU.
• Vector base register to relocate the exception-vector table
• Optimized for high-level language constructs