Freescale Semiconductor MCF5480 - Manual (Page 209)

Floating-Point Exceptions
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 6-19
A floating-point arithmetic exception becomes pending when the result of a floating-point instruction sets
an FPSR[EXC] bit and the corresponding FPCR[ENABLE] bit is set. A user write to the FPSR or FPCR
that causes the setting of an exception bit in FPSR[EXC] along with its corresponding exception enabled
in FPCR, leaves the FPU in an exception-pending state. The corresponding exception is taken at the start
of the next arithmetic instruction as a pre-instruction exception.
Executing a single instruction can generate multiple exceptions. When multiple exceptions occur with
exceptions enabled for more than one exception class, the highest priority exception is reported and taken.
It is up to the exception handler to check for multiple exceptions. The following multiple exceptions are
possible:
• Operand error (OPERR) and inexact result (INEX)
• Overflow (OVFL) and inexact result (INEX)
• Underflow (UNFL) and inexact result (INEX)
• Divide-by-zero (DZ) and inexact result (INEX)
• Input denormalized number (IDE) and inexact result (INEX)
• Input not-a-number (INAN) and input denormalized number (IDE)
In general, all exceptions behave similarly. If the exception is disabled when the exception condition
exists, no exception is taken, a default result is written to the destination (except for BSUN exception,
which has no destination), and execution proceeds normally.
If an enabled exception occurs, the same default result above is written for pre-instruction exceptions but
no result is written for post-instruction exceptions.
An exception handler is expected to execute FSAVE as its first floating-point instruction. This also clears
FPCR, which keeps exceptions from occurring during the handler. Because the destination is overwritten
for floating-point register destinations, the original floating-point destination register value is available for
the handler on the FSAVE state frame. The address of the instruction that caused the exception is available
in the FPIAR. When the handler is done, it should clear the appropriate FPSR exception bit on the FSAVE
state frame, then execute FRESTORE. If the exception status bit is not cleared on the state frame, the same
exception occurs again.
Alternatively, instead of executing FSAVE, an exception handler could simply clear appropriate FPSR
exception bits, optionally alter FPCR, and then return from the exception. Note that exceptions are never
taken on FMOVE to or from the status and control registers and FMOVEM to or from the floating-point
data registers.
At the completion of the exception handler, the RTE instruction must be executed to return to normal
instruction flow.
6.6.1.1 Branch/Set on Unordered (BSUN)
A BSUN results from performing an IEEE nonaware conditional test associated with the FBcc instruction
when an unordered condition is present. Any pending floating-point exception is first handled by a
pre-instruction exception, after which the conditional instruction restarts. The conditional predicate is
evaluated and checked for a BSUN exception before executing the conditional instruction. A BSUN
exception occurs if the conditional predicate is an IEEE non-aware branch and FPCC[NAN] is set. When
this condition is detected, FPSR[BSUN] is set.