3 pc breakpoint asid control register (pbac), Pc breakpoint asid control register (pbac) -14 – Freescale Semiconductor MCF5480 User Manual
Page 264
MCF548x Reference Manual, Rev. 3
8-14
Freescale Semiconductor
8.4.3
PC Breakpoint ASID Control Register (PBAC)
The PBAC configures the breakpoint qualification for each PC breakpoint register (PBR, PBR1, PBR2,
and PBR3). Four bits are dedicated for each breakpoint register and specify how the ASID is used in PC
breakpoint qualification.
PBR3AC, PBR2AC, PBR1AC, and PBRAC apply to PBR3, PBR2, PBR1, and PBR, respectively, and are
functionally identical. They enable or disable ASID, supervisor mode, and user mode breakpoint
6
NPL
Non-pipelined mode. Determines whether the core operates in pipelined or mode.
0 Pipelined mode
1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap.
This adds at least 5 cycles to the execution time of each instruction. Superscalar instruction
dispatch is disabled when operating in this mode. Given an average execution latency of 1.6,
throughput in non-pipeline mode would be 6.6, approximately 25% or less of pipelined
performance.
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering
instruction executes. In normal pipeline operation, the occurrence of an address or data breakpoint
trigger is imprecise. In non-pipeline mode, triggers are always reported before the next instruction
begins execution and trigger reporting can be considered precise.
An address or data breakpoint should always occur before the next instruction begins execution.
Therefore, the occurrence of the address/data breakpoints should be guaranteed.
5
—
Reserved, should be cleared.
4
SSM
Single-step mode. Setting SSM puts the processor in single-step mode.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any
BDM command can be executed. On receipt of the
GO
command, the processor executes the
next instruction and halts again. This process continues until SSM is cleared.
3
OTE
Ownership-trace enable.
1 The display of the ASID on the PSTDDATA outputs by entering in user mode, by loading the
ASID by a MOVEC, or by executing a BDM SYNC_PC command.
3–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PBR3AC
PBR2AC
PBR1AC
PBRAC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
CPU + 0x0A
Figure 8-7. PC Breakpoint ASID Control Register (PBAC)
Table 8-8. CSR Field Descriptions (Continued)
Bits
Name
Description