2 sec sequential access control register (secsacr) – Freescale Semiconductor MCF5480 User Manual
Page 320
MCF548x Reference Manual, Rev. 3
9-4
Freescale Semiconductor
9.3.1.2
SEC Sequential Access Control Register (SECSACR)
This register is used to control bus accesses to the SEC module. If a sequential accesses to the SEC are
enabled, then data will be buffered to create a single 64-bit access to the SEC instead of splitting up the
transfer into two longwords. This can help to improve overall SEC performance.
29
CPU2DMA ColdFire V4e control of the multichannel DMA breakpoint. This bit controls whether a ColdFire
V4e halt condition causes the assertion of the DMA breakpoint.
0 A ColdFire V4e halt condition will not halt the DMA.
1 A ColdFire V4e halt condition will halt the DMA.
28
DMA2CPU DMA control of the ColdFire V4e breakpoint. This bit controls whether a DMA halt condition
causes the assertion of the ColdFire V4e breakpoint.
0 A DMA halt condition will not halt the ColdFire V4e.
1 A DMA halt condition will halt the ColdFire V4e.
27
PIN2DSPI
Pin control of the DSPI breakpoint. This bit controls whether the BKPT pin can halt the DSPI.
0 The assertion of BKPT will not halt the DSPI.
1 The assertion of BKPT will halt the DSPI.
26-0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SEQEN
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x38
Figure 9-3. SEC Sequential Access Control Register (SECSACR)
Table 9-3. SECSACR Field Descriptions
Bits
Name
Description
31–1
—
Reserved
0
SEQEN
SEC Sequential access enable.
0 SEC Sequential Access is disabled.
1 SEC Sequential Access is enabled.
Note: Setting this bit is recommended when the SEC is in use.
Table 9-2. SBCR Field Descriptions (Continued)
Bit
Name
Description