Freescale Semiconductor MCF5480 - Manual (Page 326)

MCF548x Reference Manual, Rev. 3
10-4 Freescale Semiconductor
Figure 10-3. Address and Data Tenures
The following outlines the basic functions of each of the phases:
• Address tenure:
— Arbitration: During arbitration, address bus arbitration signals are used to gain mastership of
the address bus.
— Transfer: After mastership is obtained, the address bus master transfers the address and transfer
attributes on the address bus. Address signals and transfer attribute signals control the address
transfer.
— Termination: After the address transfer, the system signals that the address tenure is complete
or that it must be repeated.
• Data tenure:
— Arbitration: To begin a data tenure, the master arbitrates for data bus mastership.
— Transfer: After mastership is obtained, the data bus master samples the data bus for read
operations or drives the data bus for write operations.
— Termination: Data termination signals are required after each data beat in a data transfer. In a
single-beat transaction, data termination signals also indicate the end of the tenure; in burst
accesses, data termination signals apply to individual beats and indicate the end of the tenure
only after the final data beat.
10.1.6.2 Address Pipelines
The XLB protocol provides independent address and data bus capability to support pipeline and split-bus
transaction system organizations.
The XLB arbiter allows for one level of pipeline. This feature can be enabled and disabled in the Arbiter
Configuration Register (XARB_CFG). While this feature does not improve latency, it can significantly
improve bus/memory throughput, so it should be considered for systems that expect to stress bus
throughput capacity.
The XLB arbiter effects pipelines by regulating address bus grant, data bus grants, and address
acknowledge signals. For example, a one-level pipeline is enabled by asserting the address acknowledge
signal to the current address bus master, as well as granting the address bus to the next requesting master
before the current data bus tenure completes.
Arbitration Transfer Termination
Address Tenure
Arbitration Transfer Termination
Data Tenure