Freescale Semiconductor MCF5480 - Manual (Page 347)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 11-7
11.3.4 GPT Status Register (GSRn)
7–1 — Reserved. Should be cleared.
0 LOAD Bit forces immediate period update. Bit auto clears itself. A new period begins immediately with the
current count and width settings.
If LOAD = 0, new count or width settings are not updated until end of current period.
Prescale setting is not part of this process. Changing prescale value while PWM is active causes
unpredictable results for the period in which it was changed. The same is true for PWMOP bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CAPTURE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 OVF 0 0 0 PIN 0 0 0 0 TEXP PWMP COMP CAPT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x80C (GSR0), 0x81C (GSR1), 0x82C (GSR2), 0x83C (GSR3)
Figure 11-4. GPT Status Register (GSRn)
Table 11-5. GSRn Field Descriptions
Bits Name Description
31–16 CAPTURE Read of internal counter, latch at reference event. This is pertinent only in IC mode, in which case
it represents the count value at the time the input event occurred. Capture status does not shadow
the internal counter while an event is pending, it is updated only at the time the input event occurs.
If ICT is set to 11, which is Pulse Capture Mode, the Capture value records the width of the pulse.
Also, the SC bit is irrelevant in Pulse Capture Mode, operation is as if SC were 0.
15 — Reserved. Should be cleared.
14–12 OVF Overflow counter. Represents how many times internal counter has rolled over. This is pertinent
only during IC mode and would represent an extremely long period of time between input events.
However, if SC = 1 (indicating cumulative reporting of input events), this field could come into play.
This field is cleared by any “sticky bit” status write in the TEXP, PWMP, COMP, or CAPT bit fields.
11–9 — Reserved
8 PIN GPIO input value. This bit reflects the registered state of the TINn pin (all modes). The clock
registers the state of the input. Valid, even if timer is not enabled.
7–4 — Reserved. Should be cleared.
3 TEXP Timer expired in internal timer mode. Cleared by writing 1 to this bit position. Also cleared if TMS
is 000 (i.e., timer not enabled).
Table 11-4. GPWMn Field Descriptions (Continued)
Bits Name Description