Freescale Semiconductor MCF5480 - Manual (Page 407)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor i
Part III
On-Chip Integration
Part III describes on-chip integration for the MCF548x device. It includes descriptions of the system
SRAM, SDRAM controller, PCI, FlexBus interface, FlexCAN, SEC cryptography accelerator, and JTAG.
Contents
Part III contains the following chapters:
• Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM
implementation. It covers general operations, configuration, and initialization.
• Chapter 17, “FlexBus,” describes data transfer operations, error conditions, and reset operations.
It describes transfers initiated by the MCF548x and by an external master, and includes detailed
timing diagrams showing the interaction of signals in supported bus operations.
• Chapter 18, “SDRAM Controller (SDRAMC),” describes configuration and operation of the
synchronous DRAM controller component of the SIU. It includes a description of signals involved
in DRAM operations, including chip select signals and their address, mask, and control registers.
• Chapter 19, “PCI Bus Controller,” details the operation of the PCI bus controller for the MCF548x.
• Chapter 20, “PCI Bus Arbiter Module,” describes the MCF548x PCI bus arbiter module, including
timing for request and grant handshaking, the arbitration process, and the register in the PCI bus
arbiter programing model.
• Chapter 21, “FlexCAN,” describes the MCF548x implementation of the controller area network
(CAN) protocol. This chapter describes FlexCAN module operation and provides a programming
model.
• Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x security
encryption controller.
• Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the
MCF548x JTAG test implementation. It describes the use of JTAG instructions and provides
information on how to disable JTAG functionality.